PCI4450 datasheet(23/197 Pages) TI

23 / 197 page

PCI4450 GFN/GJG

PC Card and OHCI Controller

SCPS046 – JANUARY 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

terminal functions (continued)

Table 17. IEEE1394 PHY/Link Interface Terminals

TERMINAL

I/O

FUNCTION

NAME

GFN NO.

GJG NO.

I/O

TYPE

FUNCTION

PHY_CTL1

PHY_CTL0

I/O

Phy–link interface control. These bi-direction signals control passage of

information between the PHY and link. The link can only drive these terminals

after the PHY has granted permission following a link request (LREQ).

PHY_DATA7

PHY_DATA6

PHY_DATA5

PHY_DATA4

PHY_DATA3

PHY_DATA2

PHY_DATA1

PHY_DATA0

I/O

Phy–linkinterface data. These bi-directional signals pass data between the PHY

and link. These terminals are driven by the link on transmissions and are driven

by the PHY on receptions. Only DATA1–DATA0 are valid for 100 Mbit speed.

DATA4–DATA0 are valid for 200 Mbit speed and DATA7–DATA0 are valid for

400 Mbit speed.

PHY CLK

System clock. This input provides a 49.152 MHz clock signal for data

PHY_CLK

System clock. This in ut

rovides a 49.152 MHz clock signal for data

synchronization.

PHY_LREQ

Link request. This signal is driven by the link to initiate a request for the PHY to

perform some service.

LINKON

1394 link on. This input from the PHY indicates that the link should turn on.

LPS

Link power status. LPS indicates that link is powered and fully functional.

I/O characteristics

Figure 3 shows a 3-state bidirectional buffer illustration for reference. The table,

recommended operating

conditions provides the electrical characteristics of the inputs and outputs. The PCI4450 meets the ac

specifications of the PC Card 95 Standard and the PCI Bus 2.1 specifications.

Tied for Open Drain

Pad

VCCP

Figure 3. 3-State Bidirectional Buffer

clamping voltages

The I/O sites can be pulled through a clamping diode to a voltage rail for protection. The 3.3-V core power supply

is independent of the clamping voltages. The clamping (protection) diodes are required if the signaling

environment on an I/O is system dependent. For example, PCI signaling can be either 3.3 Vdc or 5.0 Vdc, and

the PCI4450 must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V buffer with

a clamping diode to VCCP. If a system design requires a 5.0-V PCI bus, then the VCCP would be connected to

the 5.0-V power supply.

A standard die has only one clamping voltage for the sites as shown in Figure 3. After the terminal assignments

are fixed, the fabrication facility will support a design by splitting the clamping voltage for customization. The

PCI4450 requires five separate clamping voltages since it supports a wide range of features. The five voltages

are listed and defined in the table,

recommended operating conditions.

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