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PCI4450 Datasheet(PDF) 44 Page - Texas Instruments |
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PCI4450 Datasheet(HTML) 44 Page - Texas Instruments |
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44 / 197 page ![]() PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 24. Functions 0 and 1 PCI Configuration Register Map REGISTER NAME OFFSET Device ID Vendor ID 00h Status Command 04h Class code Revision ID 08h BIST Header type Latency timer Cache line size 0Ch CardBus socket registers/ExCA base address 10h Secondary status Reserved Capabilitypointer 14h CardBus latency timer Subordinate bus number CardBus bus number PCI bus number 18h CardBus memory base register 0 1Ch CardBus memory limit register 0 20h CardBus memory base register 1 24h CardBus memory limit register 1 28h CardBus I/O base register 0 2Ch CardBus I/O limit register 0 30h CardBus I/O base register 1 34h CardBus I/O limit register 1 38h Bridge control † Interrupt pin Interrupt line 3Ch Subsystem ID ‡ Subsystem vendor ID ‡ 40h PC Card 16-bit I/F legacy mode base address ‡ 44h Reserved 48h–7Fh System control ‡ 80h Reserved Reserved General status † Multimedia control ‡ 84h GP0 control ‡ GP1 control ‡ GPE enable ‡ GPE status ‡ 88h Multifunction routing † 8Ch Diagnostic ‡ Device control ‡ Card control ‡ Retry status ‡ 90h Socket DMA register 0 ‡ 94h Socket DMA register 1 ‡ 98h Reserved 9Ch Power management capabilities † Next pointer item Capability ID A0h Data (Reserved) PMCSR bridge support extensions Power management control/status † A4h Reserved GPE control/status ‡ A8h † Oneor more bits in the register are PME context bits and can only be cleared by the assertion of G_RST when PME is enabled. If PMEisnotenabled, then these bits are cleared by the assertion of PRST or G_RST. ‡ One or more bits in this register are only cleared by the assertion G_RST. |
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