PCI4450 datasheet(79/197 Pages) TI

79 / 197 page

PCI4450 GFN/GJG

PC Card and OHCI Controller

SCPS046 – JANUARY 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

power management control/status register

Bit

15†

8†

Name

Power management control/status

Type

R/WC

R/W

Default

Power management control/status

Type:

Read-only, Read/Write, Read/Write to Clear

Offset:

A4h (Functions 0, 1)

Default:

000000h

Description: This register determines and changes the current power state of the PCI4450 CardBus

function. The contents of this register are not affected by the internally generated reset

caused by the transition from the D3hot to D0 state.

All PCI registers, ExCA registers, and CardBus registers are reset as a result of a D3hot-to-D0

state transition, with the exception of the PME context bits (if PME is enabled) and the G_RST

only bits.

Table 46. Power Management Control/Status Register Description

BIT

TYPE

FUNCTION

15†

R/WC

PMESTAT. PME status. This bit is set when the CardBus function would normally assert the PME signal, independent of

the state of the PME_EN bit. This bit is cleared by a write back of 1, and this also clears the PME signal if PME was asserted

by this function. Writing a 0 to this bit has no effect.

14–13

DATASCALE. This 2-bit field returns 0s when read. The CardBus function does not return any dynamic data, as indicated

by the DYN_DATA bit.

12–9

DATASEL. Data select. This 4-bit field returns 0s when read. The CardBus function does not return any dynamic data, as

indicated by the DYN_DATA bit.

8†

R/W

PME enable. This bit enables the function to assert PME. If this bit is cleared, then assertion of PME is disabled. This bit

will not be cleared by the assertion of PRST. It will only be cleared by the assertion of G_RST.

7–2

Reserved. These bits return 0s when read.

1–0

R/W

PWRSTATE. Power state. This 2-bit field is used both to determine the current power state of a function and to set the

function into a new power state. This field is encoded as:

00 = D0

01 = D1

10 = D2

11 = D3hot

† This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST

or G_RST.

PCI4450 Datasheet(PDF) 79 Page - Texas Instruments

PCI4450 Datasheet(HTML) 79 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL