PCI4450 datasheet(13/197 Pages) TI

13 / 197 page

PCI4450 GFN/GJG

PC Card and OHCI Controller

SCPS046 – JANUARY 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

terminal functions (continued)

Table 7. PCI Interface Control

TERMINAL

I/O

FUNCTION

NAME

GFN NO.

GJG NO.

I/O

TYPE

FUNCTION

DEVSEL

U19

I/O

PCI device select. The PCI4450 asserts DEVSEL to claim a PCI cycle as the target device.

As a PCI initiator on the bus, the PCI4450 monitors DEVSEL until a target responds. If no

target responds before timeout occurs, then the PCI4450 terminates the cycle with an

initiator abort.

FRAME

V20

T18

I/O

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to

indicate that a bus transaction is beginning, and data transfers continue while this signal

is asserted. When FRAME is deasserted, the PCI bus transaction is in the final data phase.

GNT

K20

K14

PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI4450 access to the PCI

bus after the current data transaction has completed. GNT may or may not follow a PCI

bus request, depending on the PCI bus parking algorithm.

LOCK

(MFUNC7)

P20

N19

I/O

PCI bus lock. MFUNC7/LOCK can be configured as PCI LOCK and used to gain exclusive

access downstream. Since this functionality is not typically used, other functions may be

accessed through this terminal. MFUNC7/LOCK defaults to and can be configured

through the multifunction routing status register.

IDSEL/MFUNC7

P20

N19

Initialization device select. IDSEL selects the PCI4450 during configuration space

accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI

bus. If the LATCH terminal (W12/W11) has an external pulldown resistor, then this

terminal is configurable as MFUNC7 and IDSEL defaults to the AD23 terminal.

IRDY

T17

T19

I/O

PCIinitiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data

phase of the transaction. A data phase is completed on a rising edge of PCLK where both

IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait

states are inserted.

PERR

W20

V18

I/O

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity

does not match PAR when PERR is enabled through bit 6 of the command register.

REQ

L20

L14

PCI bus request. REQ is asserted by the PCI4450 to request access to the PCI bus as an

initiator.

SERR

Y20

W18

PCI system error. SERR is an output that is pulsed from the PCI4450 when enabled through

the command register, indicating a system error has occurred. The PCI4450 need not be

the target of the PCI cycle to assert this signal. When SERR is enabled in the bridge control

CardBus interface.

STOP

V19

I/O

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the

current PCI bus transaction. STOP is used for target disconnects and is commonly

asserted by target devices that do not support burst data transfers.

TRDY

U18

I/O

PCI target ready. TRDY indicates the primary bus target’s ability to complete the current

data phase of the transaction. A data phase is completed on a rising edge of PCLK when

both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states

are inserted.

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