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PCI4450 Datasheet(PDF) 49 Page - Texas Instruments

Part # PCI4450
Description  PC Card and OHCI Controller
PDF  197 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PCI4450 Datasheet(HTML) 49 Page - Texas Instruments

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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
49
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
latency timer register
Bit
7
6
5
4
3
2
1
0
Name
Latency timer
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Register:
Latency timer
Type:
Read/Write
Offset:
0Dh
Default:
00h
Description: This register specifies the latency timer for the PCI4450, in units of PCI clock cycles. When
the PCI4450 is a PCI bus initiator and asserts FRAME, the latency timer begins counting from
zero. If the latency timer expires before the PCI4450 transaction has terminated, then the
PCI4450 terminates the transaction when its GNT is deasserted.
header type register
Bit
7
6
5
4
3
2
1
0
Name
Header type
Type
R
R
R
R
R
R
R
R
Default
1
0
0
0
0
0
1
0
Register:
Header type
Type:
Read-only
Offset:
0Eh (Functions 0, 1)
Default:
82h
Description: This register returns 82h when read, indicating that the PCI4450 functions 0 and 1
configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI
header ranges from PCI register 0 to 7Fh, and 80h–FFh is user definable extension registers.
BIST register
Bit
7
6
5
4
3
2
1
0
Name
BIST
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Register:
BIST
Type:
Read-only
Offset:
0Fh (Functions 0, 1)
Default:
00h
Description: Since the PCI4450 does not support a built-in self-test (BIST), this register returns the value of
00h when read. This register returns 0s for the two PCI4450 functions.



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