PCI4450 datasheet(93/197 Pages) TI

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PCI4450 GFN/GJG

PC Card and OHCI Controller

SCPS046 – JANUARY 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

ExCA I/O window control register (Index 07h)

Bit

Name

ExCA I/O window control

Type

R/W

Default

ExCA I/O window control

Type:

Read/Write

Offset:

CardBus Socket Address + 807h:

Card A ExCA Offset 07h

Card B ExCA Offset 47h

Default:

00h

Description: This register contains parameters related to I/O window sizing and cycle timing.

Table 57. ExCA I/O Window Control Register Description

BIT

TYPE

FUNCTION

R/W

WAITSTATE1. I/O window 1 wait-state. This bit controls the I/O window 1 wait-state for 16-bit I/O accesses. This bit has

no effect on 8-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF.

This bit is encoded as:

0 = 16-bit cycles have standard length (default)

1 = 16-bit cycles extended by one equivalent ISA wait state

R/W

ZEROWS1. I/O window 1 zero wait-state. This bit controls the I/O window 1 wait-state for 8-bit I/O accesses.

NOTE: This bit has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF.

0 = 8-bit cycles have standard length (default)

1 = 8-bit cycles reduced to equivalent of three ISA cycles

R/W

IOSIS16W1. I/O window 1 IOIS16 source. This bit controls the I/O window automatic data sizing feature which used the

IOIS16 signal from the PC Card to determine the data width of the I/O data transfer.

0 = Data width determined by DATASIZE1, bit 4 (default)

1 = Window data width determined by IOIS16

R/W

DATASIZE1.I/O window 1 data size. This bit controls the I/O window 1 data size. This bit is ignored if the I/O window 1 IOIS16

source bit (bit 5) is set. This bit is encoded as:

0 = Window data width is 8 bits (default)

1 = Window data width is 16 bits

R/W

WAITSTATE0. I/O window 0 wait-state. This bit controls the I/O window 0 wait-state for 16-bit I/O accesses. This bit has

no effect on 8-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF.

This bit is encoded as:

0 = 16-bit cycles have standard length (default)

1 = 16-bit cycles extended by one equivalent ISA wait state

R/W

ZEROWS0. I/O window 0 zero wait-state. This bit controls the I/O window 0 wait-state for 8-bit I/O accesses.

NOTE: This bit has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF.

0 = 8-bit cycles have standard length (default)

1 = 8-bit cycles reduced to equivalent of three ISA cycles

R/W

IOIS16W0. I/O window 0 IOIS16 source. This bit controls the I/O window automatic data sizing feature which used the

IOIS16 signal from the PC Card to determine the data width of the I/O data transfer.

0 = Data width determined by DATASIZE0, bit 0 (default)

1 = Window data width determined by IOIS16

R/W

DATASIZE0.I/O window 0 data size. This bit controls the I/O window 1 data size. This bit is ignored if the I/O window 1 IOIS16

Source bit (bit 1) is set. This bit is encoded as:

0 = Window data width is 8 bits (default)

1 = Window data width is 16 bits

PCI4450 Datasheet(PDF) 93 Page - Texas Instruments

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