SM320C6201GLE datasheet(39/73 Pages) TI

39 / 73 page

SM320C6201, SMJ320C6201B

DIGITAL SIGNAL PROCESSORS

SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK)

(see Figure 17) (’C6201B)

’C6201B-150

’C6201B-200

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

tsu(EDV-SSCLKH)

Setup time, read EDx valid before SSCLK high

4.2

2.5

th(SSCLKH-EDV)

Hold time, read EDx valid after SSCLK high

1.5

switching characteristics for synchronous-burst SRAM cycles† (half-rate SSCLK)

(see Figure 17 and Figure 18) (’C6201B)

PARAMETER

’C6201B-150

’C6201B-200

UNIT

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

tsu(CEV-SSCLKH)

Setup time, CEx

valid before SSCLK high

1.5P – 5.5

1.5P – 3

toh(SSCLKH-CEV)

Output hold time, CEx valid

after SSCLK high

0.5P – 2.4

0.5P – 1.5

tsu(BEV-SSCLKH)

Setup time, BEx

valid before SSCLK high

1.5P – 5.5

1.5P – 3

toh(SSCLKH-BEIV)

Output hold time, BEx invalid after SSCLK high

0.5P – 2.4

0.5P – 1.5

tsu(EAV-SSCLKH)

Setup time, EAx

valid before SSCLK high

1.5P – 5.5

1.5P – 3

toh(SSCLKH-EAIV)

Output hold time, EAx invalid after SSCLK high

0.5P – 2.4

0.5P – 1.5

tsu(ADSV-SSCLKH)

Setup time, SSADS valid

before SSCLK high

1.5P – 5.5

1.5P – 3

toh(SSCLKH-ADSV)

Output hold time, SSADS valid after SSCLK high

0.5P – 2.4

0.5P – 1.5

tsu(OEV-SSCLKH)

Setup time, SSOE valid before SSCLK high

1.5P – 5.5

1.5P – 3

toh(SSCLKH-OEV)

Output hold time, SSOE valid after SSCLK high

0.5P – 2.4

0.5P – 1.5

tsu(EDV-SSCLKH)

Setup time, EDx valid before SSCLK high

1.5P – 5.5

1.5P – 3

toh(SSCLKH-EDIV)

Output hold time, EDx invalid after SSCLK high

0.5P – 2.4

0.5P – 1.5

tsu(WEV-SSCLKH)

Setup time, SSWE valid before SSCLK high

1.5P – 5.5

1.5P – 3

toh(SSCLKH-WEV)

Output hold time, SSWE valid after SSCLK high

0.5P – 2.4

0.5P – 1.5

† The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SSCLK duty cycle.

P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

SM320C6201GLE Datasheet(PDF) 39 Page - Texas Instruments

SM320C6201GLE Datasheet(HTML) 39 Page - Texas Instruments

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