SM320C6201GLE datasheet(67/73 Pages) TI

67 / 73 page

SM320C6201, SMJ320C6201B

DIGITAL SIGNAL PROCESSORS

SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 37)

(’C6201B)

’C6201B-150

’C6201B-200

UNIT

NO.

MASTER

SLAVE

UNIT

MIN

MAX

MIN

MAX

tsu(DRV-CKXL)

Setup time, DR valid before CLKX low

3P – 2

th(CKXL-DRV)

Hold time, DR valid after CLKX low

5 + 6P

† The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency

in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.

‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡

(see Figure 37) (’C6201B)

PARAMETER

’C6201B-150

’C6201B-200

UNIT

NO.

PARAMETER

MASTER§

SLAVE

UNIT

MIN

MAX

MIN

MAX

th(CKXH-FXL)

Hold time, FSX low after CLKX high¶

H – 2

H + 3

td(FXL-CKXL)

Delay time, FSX low to CLKX low#

T – 2

T + 1

td(CKXH-DXV)

Delay time, CLKX high to DX valid

–2

3P + 4

5P + 17

tdis(CKXH-DXHZ)

Disable time, DX high impedance following last data bit from

CLKX high

–2

3P + 3

5P + 17

td(FXL-DXV)

Delay time, FSX low to DX valid

L – 2

L + 4

2P + 2

4P + 17

† The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency

in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.

‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

§ T = CLKX period = (1 + CLKGDV) * P; if CLKSM = 1, then P = 1/CPU clock frequency

CLKX period = (1 + CLKGDV) * P_clks; if CLKSM = 0, then P_clks = CLKS period.

H =

CLKX high pulse width = (CLKGDV/2 + 1) * T

L =

CLKX low pulse width = (CLKGDV/2) * T

¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

SM320C6201GLE Datasheet(PDF) 67 Page - Texas Instruments

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