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SM320C6201GLE Datasheet(PDF) 6 Page - Texas Instruments

Part # SM320C6201GLE
Description  DIGITAL SIGNAL PROCESSORS
PDF  73 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SM320C6201GLE Datasheet(HTML) 6 Page - Texas Instruments

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SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
SIGNAL
TYPE†
DESCRIPTION
NAME
NO.
TYPE†
DESCRIPTION
EMIF – SYNCHRONOUS BURST SRAM CONTROL
SSADS
V8
O/Z
SBSRAM address strobe
SSOE
W7
O/Z
SBSRAM output enable
SSWE
Y7
O/Z
SBSRAM write enable
SSCLK
AA8
O/Z
SBSRAM clock
EMIF – SYNCHRONOUS DRAM CONTROL
SDA10
V7
O/Z
SDRAM address 10 (separate for deactivate command)
SDRAS
V6
O/Z
SDRAM row address strobe
SDCAS
W5
O/Z
SDRAM column address strobe
SDWE
T8
O/Z
SDRAM write enable
SDCLK
T9
O/Z
SDRAM clock
EMIF – BUS ARBITRATION
HOLD
R6
I
Hold request from the host
HOLDA
B15
O
Hold request acknowledge to the host
TIMERS
TOUT1
G2
O/Z
Timer 1 or general-purpose output
TINP1
K3
I
Timer 1 or general-purpose input
TOUT0
M18
O/Z
Timer 0 or general-purpose output
TINP0
J18
I
Timer 0 or general-purpose input
DMA ACTION COMPLETE
DMAC3
E18
DMAC2
F19
O
DMA action complete
DMAC1
E20
O
DMA action complete
DMAC0
G16
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1
F4
I
External clock source (as opposed to internal)
CLKR1
H4
I/O/Z
Receive clock
CLKX1
J4
I/O/Z
Transmit clock
DR1
E2
I
Receive data
DX1
G4
O/Z
Transmit data
FSR1
F3
I/O/Z
Receive frame sync
FSX1
F2
I/O/Z
Transmit frame sync
† I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground



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