SM320C6201GLE datasheet(63/73 Pages) TI

63 / 73 page

SM320C6201, SMJ320C6201B

DIGITAL SIGNAL PROCESSORS

SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 36)

(’C6201)

’C6201-150

NO.

MASTER

SLAVE

UNIT

MIN

MAX

MIN

MAX

tsu(DRV-CKXH) Setup time, DR valid before CLKX high

12*

3P – 2

th(CKXH-DRV)

Hold time, DR valid after CLKX high

5 + 6P

† The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency

in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.

‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

*This parameter is not production tested.

switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡

(see Figure 36) (’C6201)

’C6201-150

NO.

PARAMETER

MASTER§

SLAVE

UNIT

MIN

MAX

MIN

MAX

th(CKXH-FXL)

Hold time, FSX low after CLKX high¶

T – 2*

T + 3*

td(FXL-CKXL)

Delay time, FSX low to CLKX low#

H – 2*

H + 4.5*

td(CKXL-DXV)

Delay time, CLKX low to DX valid

This is also specified by design but not tested to be the

delay time for data to be low impedance on the first

data bit.

–2*

3P + 4*

5P + 17*

tdis(CKXH-DXHZ)

Disable time, DX high impedance following last data bit

from CLKX high

H – 2*

H + 3*

tdis(FXH-DXHZ)

Disable time, DX high impedance following last data bit

from FSX high

P + 4*

3P + 17*

td(FXL-DXV)

Delay time, FSX low to DX valid

2P + 4*

4P + 17*

† The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency

in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.

‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

§ T = CLKX period = (1 + CLKGDV) * P ; if CLKSM = 1, then P = 1/CPU clock frequency

CLKX period = (1 + CLKGDV) * P_clks; if CLKSM = 0, then P_clks = CLKS period.

H =

CLKX high pulse width = (CLKGDV/2 + 1) * T

L =

CLKX low pulse width = (CLKGDV/2) * T

¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

*This parameter is not production tested.

# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

SM320C6201GLE Datasheet(PDF) 63 Page - Texas Instruments

SM320C6201GLE Datasheet(HTML) 63 Page - Texas Instruments

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