SM320C6201GLE datasheet(42/73 Pages) TI

42 / 73 page

SM320C6201, SMJ320C6201B

DIGITAL SIGNAL PROCESSORS

SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

SYNCHRONOUS DRAM TIMING (CONTINUED)

timing requirements for synchronous DRAM cycles (see Figure 19) (’C6201B)

’C6201B-150

’C6201B-200

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

tsu(EDV-SDCLKH)

Setup time, read EDx valid before SDCLK high

1.5

th(SDCLKH-EDV)

Hold time, read EDx valid after SDCLK high

switching characteristics for synchronous DRAM cycles† (see Figure 19–Figure 24) (’C6201B)

PARAMETER

’C6201B-150

’C6201B-200

UNIT

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

tsu(CEV-SDCLKH)

Setup time, CEx valid

before SDCLK high

1.5P – 6

1.5P – 3.5

toh(SDCLKH-CEV)

Output hold time, CEx valid after SDCLK high

0.5P – 2

0.5P – 1

tsu(BEV-SDCLKH)

Setup time, BEx valid

before SDCLK high

1.5P – 6

1.5P – 3.5

toh(SDCLKH-BEIV)

Output hold time, BEx

invalid after SDCLK high

0.5P – 2

0.5P – 1

tsu(EAV-SDCLKH)

Setup time, EAx valid

before SDCLK high

1.5P – 6

1.5P – 3.5

toh(SDCLKH-EAIV)

Output hold time, EAx

invalid after SDCLK high

0.5P – 2

0.5P – 1

tsu(SDCAS-SDCLKH)

Setup time, SDCAS valid

before SDCLK high

1.5P – 6

1.5P – 3.5

toh(SDCLKH-SDCAS)

Output hold time, SDCAS valid after SDCLK high

0.5P – 2

0.5P – 1

tsu(EDV-SDCLKH)

Setup time, EDx valid

before SDCLK high

1.5P – 6

1.5P – 3.5

toh(SDCLKH-EDIV)

Output hold time, EDx

invalid after SDCLK high

0.5P – 2

0.5P – 1

tsu(SDWE-SDCLKH)

Setup time, SDWE valid

before SDCLK high

1.5P – 6

1.5P – 3.5

toh(SDCLKH-SDWE)

Output hold time, SDWE valid after SDCLK high

0.5P – 2

0.5P – 1

tsu(SDA10V-SDCLKH)

Setup time, SDA10 valid

before SDCLK high

1.5P – 6

1.5P – 3.5

toh(SDCLKH-SDA10IV)

Output hold time, SDA10 invalid after SDCLK

high

0.5P – 2

0.5P – 1

tsu(SDRAS-SDCLKH)

Setup time, SDRAS valid

before SDCLK high

1.5P – 6

1.5P – 3.5

toh(SDCLKH-SDRAS)

Output hold time, SDRAS valid after SDCLK high

0.5P – 2

0.5P – 1

† The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SDCLK duty cycle.

P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

SM320C6201GLE Datasheet(PDF) 42 Page - Texas Instruments

SM320C6201GLE Datasheet(HTML) 42 Page - Texas Instruments

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