TPIC44H01

4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER

SLIS088 – SEPTEMBER 1998

6

POST OFFICE BOX 655303

electrical characteristics over recommended operating case temperature and supply voltage

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I(PWR)

V(PWR)supplycurrent All outputs off, V(PWR)= 12 V

2

4

6

mA

ICCH

5-V supply current

All outputs off, VCC = 5.5 V

3

4

5

mA

Sleep state current

Sleep state (all outputs off)

I(PWR-sleep)

Slee state current

(IPWR)

Slee state (all out uts off),

VCC 55 V V(PWR) 12 V TC 25°C

15

40

µA

I(PWR-slee )

(IPWR)

VCC = 5.5 V, V(PWR) = 12 V, TC = 25°C

15

40

µA

Sleep state current

Sleep state (all outputs off)

ICCL(sleep)

Slee state current

(ICCL)

Slee state (all out uts off),

VCC 55 V V(PWR) 12 V TC 25°C

30

40

µA

ICCL(slee )

(ICCL)

VCC = 5.5 V, V(PWR) = 12 V, TC = 25°C

30

40

µA

VIT(POR)

Power-on reset

threshold, VCC

V(PWR) = 5.5 V, VCC increasing

3.4

3.9

4.4

V

Vhys(POR)

Power-on reset

threshold hysteresis,

VCC

V(PWR) = 5.5 V, VCC decreasing

100

300

500

mV

V(PWR) > 24 V, CP = 0.01 µF, CS = 0.1 µF,

40

44

V

(PWR)

,

µ ,

µ ,

I(CP) = – 2 mA, See Figure 8

40

44

V

V(PWR) =24V CP=001 µF CS=01 µF

V(PWR) = 24 V, CP = 0.01 µF, CS = 0.1 µF,

I(CP)

2 mA See Figure 8

38

40

42

V

V(CP)

Charge pump voltage

I(CP) = – 2 mA, See Figure 8

38

40

42

V

V(CP)

Charge um voltage

V(PWR) = 8 V, CP = 0.01 µF, CS = 0.1 µF,

11 5

13 5

V

(PWR)

,

µ ,

µ ,

I(CP) = – 2 mA, See Figure 8

11.5

13.5

V

V(PWR) = 5.5 V, CP = 0.01 µF,

CS = 0.1

µF, I(CP) = –2 mA, See Figure 8

6.8

7.5

V

V(OVLO)

Over-supply voltage

lockout

Gate disabled, See Figure 10

27.5

30

32.5

V

Vhys(OV)

Over-supply voltage

reset hysteresis

See Figure 10

0.5

1

2

V

8 V < V(PWR) < 24 V, IO = –100 µA,

V(PWR)+4

V(PWR)+18

V

VG

Gate drive voltage

(PWR)

, O

µ ,

All channels on, See Note 2

V(PWR)+4

V(PWR)+18

V

VG

Gate drive voltage

5.5 V < V(PWR) < 8 V, IO = –100 µA,

V(PWR)+1 5 V(PWR)+3 5

V

(PWR)

, O

µ ,

All channels on, See Note 2

V(PWR)+1.5 V(PWR)+3.5

V

VG(sleep)

External gate sleep

state voltage

IO = 100 µA, RESET = CS = 0 V

0

100

300

mV

VGS(clamp)

Gate-to-source clamp

voltage

SRCx = 0 V, Output on

15

17

19.5

V

VSG(clamp)

Source-to-gate clamp

voltage

Output off, II = 100 µA

6.5

8

9.5

V

IG(SRC )

Gate drive source

VG = 0 V, V(PWR) = 12 V

– 2.3

–3

– 3.7

mA

IG(SRCx)

current

VG = 10 V, V(PWR) = 12 V

– 1.4

–2

– 2.6

mA

IG(SNK )

Gate drive sink

VG = 2 V, V(PWR) = 12 V

1

1.5

2

mA

IG(SNKx)

current

VG= V(PWR) = 12 V

2

2.6

3.2

mA

V(open)

SRCx pin off-state

open-load detection

threshold

All outputs off, See Figure 11

1.9

2.4

2.6

V

Vhys(open)

Off-state open-load

hysteresis

All outputs off

–50

– 150

– 300

mV

† Device will function with degraded performance for a power supply voltage between 5.5 V and 8 V.

NOTE 2: For characterization purposes only, not implemented in production testing.