TPIC44H01

4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER

SLIS088 – SEPTEMBER 1998

19

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

over-current detection/protection

On-state, over-current detection is implemented in TPIC44H01 by monitoring SRCx voltage with respect to

threshold is exceeded for the entire deglitch time, a valid over-current shutdown fault (OCSD) is recognized.

If an over-current fault is detected with AR_ENBL = 0, a real-time fault condition is flagged to the host controller

by latching FLT low, the appropriate internal fault bit is set, and the GATEx output is latched off. GATEx will

remain off until the error condition has been corrected and the input bit or parallel input is cycled off then on.

An over-heating condition of the FET can occur if the host controller continually re-enables the output under

short-to-ground conditions.

If an over-current fault is detected with AR_ENBL = 1, FLT is latched low, the appropriate internal fault bit is set,

and the gate output is disabled until an auto-retry timer re-enables it. If the over-current remains, auto-retry

provides a low duty cycle PWM (

≈ 0.75%) function to protect the FET from over heating. The PWM period is

maintained until the fault has been eliminated and/or until the channel is turned off by both the INx parallel input

and the serial control bit. The host controller can read the serial port of the device to determine which channel

reported the fault condition. Fault bits (1:8) distinguish faults for each of the output channels (see Table 3).

100

Ω

Comp

V

Deglitch

Timer

OSC

V(PWR)

SRCx

+

V(OVDS)

+

–

V(OVDS)

Input

GATEx

VDS

FLT

Normal Load

Input

GATEx

VDS

FLT

Over-Current

AR_ENBL = 0

t(deglitch)

Input

GATEx

VDS

FLT

Over-Current

AR_ENBL = 1

t(retry)

V(OVDS)

V(OVDS)

t(deglitch)

<t(deglitch)

–

VDS

Figure 12. Over-Current Fault Detection