TPIC44H01

4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER

SLIS088 – SEPTEMBER 1998

16

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

performance under fault conditions

The TPIC44H01 is designed for normal operation over a supply voltage range of 8 V to 24 V with over-voltage

fault detection typically at 30 V. The device offers on board fault detection to handle a variety of faults which may

occur within a system. The primary function of the circuitry is to prevent damage to the load and the external

power FETs in the event that a fault occurs, but off-state, open-load detection and reporting is also provided for

diagnostics. Note that unused SRC1 – 4 inputs must be connected to their respective GATE1 – 4 pins to prevent

false reporting of open-load fault conditions. Unused outputs with a SRC-to-GATE short should not be

commanded on. For on-state faults, the circuitry detects the fault, shuts off the output to the FET, and reports

the fault to the microcontroller. The primary faults monitored are:

1.

2.

Open-load

3.

Over-current

4.

Short-to-ground

FLT, fault interrupt operation

The FLT pin provides a real-time fault interrupt to signal a host controller that a fault has been detected. Any

of the four fault conditions listed above causes the FLT pin to be latched low immediately upon fault detection.

NOTE:

Once FLT is latched low from a fault occurrence, it can only be cleared by a high-to-low transition

on CS.

voltage is detected above 30 V, the device will turn off all gate drive outputs to prevent possible damage to the

internal charge pump, the external FET, and the load. An OVLO fault will be flagged to the controller by FLT being

latched low. The FLT interrupt will be reset by a high-to-low transition of CS, provided that the OVLO condition

is corrected, and no other faults have been detected with internal fault bits set. Thus, the user will detect an

OVLO fault by a low transition on FLT with no fault bit read from SDO (see Table 3). The gate outputs will return

to normal operation immediately after the OVLO condition is removed (the outputs are not latched off). Figure

10 illustrates the operation of the over-supply voltage detection circuit.

_

+

30 V

29 V

12 V

V(PWR)

GATE (1–4)

OVLO Output Disable

30 V

V(PWR)

Figure 10. Over-Voltage Lockout Waveform