TPIC44H01

4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER

SLIS088 – SEPTEMBER 1998

14

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

parallel input data operation

In addition to the serial interface, the TPIC44H01 also provides a parallel interface to control gate drive outputs.

Parallel input is OR’ed with the serial interface control bit. Thus, the parallel inputs provide direct, real-time

control of the output drivers. SCLK and CS are not required to transfer parallel input data to the output buffer.

Fault detection/protection is provided during parallel operation (see

performance under fault conditions

section).

With AR_ENBL pin low, detection of an over-current or short-to-ground fault condition will disabled the gate drive

until the auto-retry timer clears and re-enables the output.

CAUTION:

If a parallel input is cycled low then high during auto-retry time, the timer is reset and the gate drive

re-enable. The device will not prevent the user from switching at a higher duty cycle than the

auto-retry function provides.

Serial fault data can be read over the serial data bus as described in the

serial data operation section. If the FLT

pin is latched low due to a fault detection, it cannot be cleared by cycling the parallel input. It can only be cleared

by a low level on CS.

In applications where the serial interface and FLT interrupt are unused, CS should be tied high to disable the

serial interface.

In applications where the serial interface or FLT interrupt are used only to retrieve fault data, care should be

taken to program the SDI input low to prevent accidental activation of a gate drive output using a serial input

control bit.

charge pump operation

The TPIC44H01 provides a charge pump circuit to generate the high-side gate drive voltage. It is a doubler using

external pump and storage capacitors, CP and CS respectively (refer to the schematic/block diagram). For

from ground (see Figure 8).

15 V

42 V

V(CP)

V(PWR)

Time

Voltage

42 V

30 V

14 V