DS1874 datasheet(28/88 Pages) MAXIM

28 / 88 page

SFP+ Controller with Digital LDD Interface

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START

STOP

SLAVE

ACK

SLAVE

ACK

STOP

SINGLE-BYTE WRITE

-WRITE 00h TO REGISTER BAh

TWO-BYTE WRITE

-WRITE C8h AND C9h

TO 01h AND 75h

SINGLE-BYTE READ

-READ REGISTER BAh

TWO-BYTE READ

-READ C8h AND C9h

REPEATED

START

MASTER

NACK

10100010

A2h

10111010

BAh

SLAVE

ACK

START

SLAVE

ACK

10100010

A2h

10100011

A3h

10111010

BAh

SLAVE

ACK

SLAVE

ACK

STOP

00000000

00h

STOP

SLAVE

ACK

STOP

01110101

75h

START

SLAVE

ACK

10100010

A2h

11001000

C8h

SLAVE

ACK

SLAVE

ACK

00000001

01h

SLAVE

ACK

DATA IN BAh

DATA

REPEATED

START

MASTER

NACK

START

SLAVE

ACK

10100010

A2h

10100011

A3h

11001000

C8h

SLAVE

ACK

SLAVE

ACK

DATA IN C8h

DATA

MASTER

NACK

DATA IN C9h

DATA

EXAMPLE I2C TRANSACTIONS WITH A2h AS THE MAIN MEMORY DEVICE ADDRESS

*IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h FOR THE MAIN MEMORY.

IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Ch FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED

ADDRESS FOR THE MAIN MEMORY IS A0h.

TYPICAL I2C WRITE TRANSACTION

MSB

LSB

MSB

LSB

DATA

SLAVE

ACK

SLAVE

ACK

SLAVE

ADDRESS*

R/W

MSB

LSB

READ/

WRITE

Figure 18. Example I2C Timing

cycle. This can result in a whole page being worn out

over time by writing a single byte repeatedly. Writing

a page one byte at a time wears the EEPROM out

eight times faster than writing the entire page at

once. The DS1874’s EEPROM write cycles are speci-

fied in the

Nonvolatile Memory Characteristics table.

The specification shown is at the worst-case temper-

ature. It can handle approximately ten times that

many writes at room temperature. Writing to SRAM-

shadowed EEPROM memory with SEEB = 1 does not

count as an EEPROM write cycle when evaluating

the EEPROM’s estimated lifetime.

Reading a single byte from a slave: Unlike the

write operation that uses the memory address byte

to define where the data is to be written, the read

operation occurs at the present value of the memory

address counter. To read a single byte from the

slave, the master generates a START condition,

writes the slave address byte with R/W = 1, reads

the data byte with a NACK to indicate the end of the

transfer, and generates a STOP condition.

Manipulating the address counter for reads: A

dummy write cycle can be used to force the address

pointer to a particular value. To do this, the master

generates a START condition, writes the slave

address byte (R/W = 0), writes the memory address

where it desires to read, generates a repeated

START condition, writes the slave address byte (R/W

= 1), reads data with ACK or NACK as applicable,

and generates a STOP condition.

Memory Organization

The DS1874 features nine separate memory tables that

are internally organized into 8-byte rows.

The Lower Memory is addressed from 00h to 7Fh and

contains alarm and warning thresholds, flags, masks,

several control registers, password entry area (PWE),

and the table-select byte.

Table 01h primarily contains user EEPROM (with PW1

level access) as well as alarm and warning-enable

bytes.

Table 02h is a multifunction space that contains config-

uration registers, scaling and offset values, passwords,

interrupt registers as well as other miscellaneous con-

trol bytes.

Table 04h contains a temperature-indexed LUT for

control of the modulation voltage. The modulation LUT

can be programmed in 2°C increments over the -40°C

to +102°C range.

DS1874 Datasheet(PDF) 28 Page - Maxim Integrated Products

DS1874 Datasheet(HTML) 28 Page - Maxim Integrated Products

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