Reset Timeout Capacitor

The reset timeout period can be adjusted to accommo-

date a variety of µP applications from 50µs to 1.12s.

reset timeout capacitor as follows:

timeout of 140ms (min).

Manual Reset Input (MR)

(MAX16001/MAX16002/

MAX16004–MAX16007)

Many µP-based products require manual reset capabil-

ity, allowing the operator, a test technician, or external

logic circuitry to initiate a reset. A logic-low on MR

asserts RESET low. RESET remains asserted while MR

is low, and during the reset timeout period (140ms min)

after MR returns high. The MR input has an internal

20k

nected if not used. MR can be driven with TTL or

CMOS-logic levels, or with open-drain/collector out-

puts. Connect a normally open momentary switch from

MR to GND to create a manual reset function. External

debounce circuitry is not required. If MR is driven from

long cables or if the device is used in a noisy environ-

ment, connecting a 0.1µF capacitor from MR to GND

provides additional noise immunity.

Margin Output Disable (

MARGIN)

MARGIN allows system-level testing while power sup-

plies are adjusted from their nominal voltages. Drive

MARGIN low to force RESET, WDO, and OUT_ high,

regardless of the voltage at any monitored input. The

state of each output does not change while MARGIN =

GND. The watchdog timer continues to run when

MARGIN is low, and if a timeout occurs, WDO/RESET

Power-Supply Bypassing

The MAX16000–MAX16007 operate from a 2.0V to 5.5V

supply. An undervoltage lockout ensures that the out-

puts are in the correct states when the UVLO is exceed-

0.1µF capacitor as close to the device as possible. The

additional capacitor improves transient immunity. For

be required

CF

ts x I

V

SRT

RP

SRT

TH SRT

()

()

_

=

Low-Voltage, Quad-/Hex-/Octal-Voltage

µP Supervisors

22

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MARGIN

RESET

INTERNAL

RESET

SIGNAL