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MB91F613 Datasheet(PDF) 3 Page - fujitsu semiconductor

Part # MB91F613
Description  32-bit Microcontrollers
PDF  104 Pages
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Manufacturer  FUJITSU [fujitsu semiconductor]
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Logo FUJITSU - fujitsu semiconductor

MB91F613 Datasheet(HTML) 3 Page - fujitsu semiconductor

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MB91610 Series
DS07-16907-2E
3
• Interrupts
• Total of 16 external interrupts (some pins are 5 V tolerant)
• Interrupts from peripheral resources
• Programmable interrupt levels (16 levels)
• Can be used to return from stop mode, sleep mode
• A/D converter
• 8 channels, 1 unit
• 10-bit resolution
• Conversion time : approx. 1.2 μs (PCLK = 33 MHz)
• Priority conversion (2 levels)
• Conversion modes : Single-shot conversion mode, scan conversion mode
• Activation sources : Software, external trigger, base timer
• Built-in FIFO for storing conversion data (for scan conversion:16, for priority conversion:4)
• Base timer
• 8 channels
• Operation mode is selectable from the followings for each channel
- 16/32-bit reload timer
- 16-bit PWM timer
- 16/32-bit PWC timer
- 16-bit PPG timer
• Cascading connection between 2 channels allows them to be used as one 32-bit timer
• Multiple channels can be started simultaneously
• Input/output select function
• 16-bit reload timer
• 3 channels (including 1 channel for REALOS)
• Interval timer function
• Count clock select function (peripheral clock (PCLK) divided by 2 to 64)
• Compare timer
• 32-bit input capture : 4 channels
• 32-bit output compare : 4 channels
• 32-bit free-run timer : 1 channel
• Other interval timers
• Watch counter : 1 channel
• Watchdog timer : 2 channels
- Watchdog timer 0
- After resetting this device, the watchdog timer becomes active when an arbitrary value is written to the
WDTCPR0 register.
- The cycle of the watchdog timer 0 can be selected from the peripheral clock (PCLK)
× (29 to 224).
- Watchdog timer 1
- After releasing the reset of this device, it counts with the CPU clock (CCLK).
- Disable/ enable of the counter operation can be controlled by HWDE pin.
- The cycle of the watchdog timer 1 is CCLK
× 223 cycle fixed.
(Continued)



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