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MB91F613 Datasheet(PDF) 32 Page - fujitsu semiconductor |
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MB91F613 Datasheet(HTML) 32 Page - fujitsu semiconductor |
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32 / 104 page ![]() MB91610 Series 32 DS07-16907-2E ■ I/O MAP [How to read the table] Notes : • When performing a data access, the addresses should be as below. - Word access : Address should be multiples of 4 (least significant 2 bits should be “00B”) - Half word access : Address should be multiples of 2 (least significant bit should be “0B”) - Byte access : ⎯ • Do not access the reserved areas. Address Register Block + 0 + 1 + 2 + 3 0000 0000H PDR0 [R/W] B, H XXXXXXXX PDR1 [R/W] B, H XXXXXXXX PDR2 [R/W] B, H XXXXXXXXXXX PDR3 [R/W] B, H XXXXXXXX Port data register 0000 003CH WDTCR0 [R/W] B, H -0--0000 WDTCPR0 [R/W] B, H 00000000 ⎯ Watchdog timer 0000 0040H EIRR0 [R/W] B, H, W 000 0000 ENIR0 [R/W] B, H, W 00000000 ELVR0 [R/W] B, H, W 00000000 00000000 External interrupt 0 to 7 Access unit ( B : byte, H : half word, W : word) Read/write attribute “R” : Indicates that there is a read only bit. “R/W” : Indicates that there is a read/write bit. “W” : Indicates that there is a write only bit. Register name (column 1 of the register is at address 4n, column 2 is at address 4 n + 2...) Leftmost register address (For word-length access, column 1 of the register is the MSB of the data.) Initial value after reset “1” : Initial value“1” “0” : Initial value“0” “X” : Initial value undefined “ - ” : Reserved bit or undefined bit ⎯ : Reserved area |
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