MCP40D18 datasheet(37/66 Pages) MICROCHIP

37 / 66 page

DS22152B-page 37

MCP40D17/18/19

5.3

Software Reset Sequence

At times it may become necessary to perform a

Software Reset Sequence to ensure the MCP40D17/

18/19 device is in a correct and known I2C Interface

state. This only resets the I2C state machine.

This is useful if the MCP40D17/18/19 device powers up

in an incorrect state (due to excessive bus noise, etc),

or if the Master Device is reset during communication.

Figure 5-11 shows the communication sequence to

software reset the device.

FIGURE 5-11:

Software Reset Sequence

Format.

The 1st Start bit will cause the device to reset from a

state in which it is expecting to receive data from the

Master Device. In this mode, the device is monitoring

the data bus in Receive mode and can detect the Start

bit forces an internal Reset.

The nine bits of ‘1’ are used to force a Reset of those

devices that could not be reset by the previous Start bit.

This occurs only if the MCP40D17/18/19 is driving an A

on the I2C bus, or is in output mode (from a Read

command) and is driving a data bit of ‘0’ onto the I2C

bus. In both of these cases, the previous Start bit could

not be generated due to the MCP40D17/18/19 holding

the bus low. By sending out nine ‘1’ bits, it is ensured

that the device will see a A (the Master Device does not

drive the I2C bus low to acknowledge the data sent by

the

MCP40D17/18/19),

which

also

forces

the

MCP40D17/18/19 to reset.

The 2nd Start bit is sent to address the rare possibility

of an erroneous write. This could occur if the Master

Device was reset while sending a Write command to

the MCP40D17/18/19, AND then as the Master Device

returns to normal operation and issues a Start condition

while the MCP40D17/18/19 is issuing an A. In this case

if the 2nd Start bit is not sent (and the Stop bit was sent)

the MCP40D17/18/19 could initiate a write cycle.

The Stop bit terminates the current I2C bus activity.

The MCP40D17/18/19 wait to detect the next Start

condition.

This sequence does not effect any other I2C devices

which may be on the bus, as they should disregard this

as an invalid command.

5.4

Serial Commands

The

MCP40D17/18/19

devices

support

serial

commands. These commands are:

• Write Operation

• Read Operations

The I2C command formats have been defined so to

support the SMBus version 2.0 Write Byte/Word

Protocol

formats

and

Read

Byte/Word

Protocol

formats.

The

SMBus

specification

defines

this

operation is Section 5 of the Version 2.0 document

(August 3, 2000).

This protocol format may be convienient for customers

using library routines for the I2C bus, where all they

need to do is specify the command (read, write, ...) with

the Device Address, the Register Address, and the

Data.

If higher data throughput is desired, please look at the

MCP4017/18/19 devices which have a simplier I2C

command format.

Note:

This technique should be supported by

any I2C compliant device. The 24XXXX

I2C Serial EEPROM devices support this

technique,

which

documented

AN1028.

Note:

The potential for this erroneous write

ONLY occurs if the Master Device is reset

while sending a Write command to the

MCP40D17/18/19.

‘1’

Start

bit

Nine bits of ‘1’

Start bit

Stop bit

MCP40D18 Datasheet(PDF) 37 Page - Microchip Technology

MCP40D18 Datasheet(HTML) 37 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL