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MCP40D18 Datasheet(PDF) 38 Page - Microchip Technology |
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MCP40D18 Datasheet(HTML) 38 Page - Microchip Technology |
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38 / 66 page ![]() MCP40D17/18/19 DS22152B-page 38 © 2009 Microchip Technology Inc. 5.4.1 WRITE OPERATION The write operation requires the START condition, Control Byte, Acknowledge, Command Code, Acknowledge, Data Byte, Acknowledge and STOP (or RESTART) condition. The Control (Slave Address) Byte requires the R/W bit equal to a logic zero (R/W = “0” ) to generate a write sequence. The MCP40D17/ 18/19 is responsible for generating the Acknowledge (A) bits. Data is written to the MCP40D17/18/19 after every byte transfer (during the A bit). If a STOP or RESTART condition is generated during a data transfer (before the A bit), the data will not be written to MCP40D17/18/ 19. Data bytes may be written after each Acknowledge. The command is terminated once a Stop (P) condition occurs. Refer to Figure 5-12 for the single byte write sequence and Figure 5-13 for the generic (multi-byte) write sequence. For a single byte write, the master sends a STOP or RESTART condition after the 1st data byte is sent. The MSb of each Data Byte is a don’t care, since the wiper register is only 7-bits wide. The command is terminated once a Stop (P) or Restart (S) condition occurs. Figure 5-14 shows the I2C write communication behavior of the Master Device and the MCP40D17/18/ 19 device and the resultant I2C bus values. 5.4.2 READ OPERATIONS The read operation requires the START condition, Control Byte, Acknowledge, Command Code, Acknowledge, Restart Condition, Control Byte, Acknowledge, Data Byte, the master generating the A and STOP (or RESTART) condition. The first Control Byte requires the R/W bit equal to a logic zero (R/W = “0” ) to write the Command Code, while the second Control Byte requires the R/W bit equal to a logic one (R/W = “1”) to generate a read sequence. The MCP40D17/18/19 will A the Slave Address Byte and A all the Data Bytes. The I2C Master will A the Slave Address Byte and the last Data Byte. If there are multiple Data Bytes, the I2C Master will A all Data Bytes except the last Data Byte (which it will A). The MCP40D17/18/19 maintains control of the SDA signal until all data bits have been clocked out. The command is terminated once a Stop (P) or Restart (S) condition occurs. Refer to Figure 5-15 for the read command sequence. For a single read, the master sends a STOP or RESTART condition after the 1st data byte (and A bit) is sent from the slave. Figure 5-16 shows the I2C read communication behavior of the Master Device and the MCP40D17/18/ 19 device and the resultant I2C bus values. FIGURE 5-12: I2C Single Byte Write Command Format (Slave Address = “0101110”). Note: A command code with a non-zero value will cause the data not to be written to the wiper register Note: A command code with a non-zero value will cause the data not to be read from the wiper register STOP bit Slave Address Byte Command Code Data Byte 1 010 S 11 0 0 0 A0 0 0 A D3 X D6 D5D4 D2D1 D0 A Fixed Address P Read/Write bit (“0” = Write) 00 0 0 S = Start Condition P = Stop Condition A = Acknowledge X = Don’t Care R/W = Read/Write bit D6:D0 = Data bits Legend |
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