ATmega324P datasheet(215/377 Pages) ATMEL

215 / 377 page

215

7674F–AVR–09/09

ATmega164P/324P/644P

Note that arbitration is not allowed between:

• A REPEATED START condition and a data bit.

• A STOP condition and a data bit.

• A REPEATED START and a STOP condition.

It is the user software’s responsibility to ensure that these illegal arbitration conditions never

occur. This implies that in multi-master systems, all data transfers must use the same composi-

tion of SLA+R/W and data packets. In other words: All transmissions must contain the same

number of data packets, otherwise the result of the arbitration is undefined.

19.5

Overview of the TWI Module

The TWI module is comprised of several submodules, as shown in Figure 19-9. All registers

drawn in a thick line are accessible through the AVR data bus.

Figure 19-9. Overview of the TWI Module

Address Register

(TWAR)

Address Match Unit

Address Comparator

Control Unit

Control Register

(TWCR)

Status Register

(TWSR)

State Machine and

Status control

SCL

Slew-rate

Control

Spike

Filter

SDA

Slew-rate

Control

Spike

Filter

Bit Rate Generator

Bit Rate Register

(TWBR)

Prescaler

Bus Interface Unit

START / STOP

Control

Arbitration detection

Ack

Spike Suppression

Address/Data Shift

ATmega324P Datasheet(PDF) 215 Page - ATMEL Corporation

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