ATmega88 datasheet(303/340 Pages) ATMEL

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7530H–AVR–02/09

ATmega48/88/168 Automotive

26.8.1

RC Oscillator Precision for LIN Slave implementation

For LIN slave devices, the precision of the RC oscillator before and after re-synchronization are

described in the Figure 26-2

27. 2-wire Serial Interface Characteristics

Table 27-1 describes the requirements for devices connected to the 2-wire Serial Bus. The ATmega48/88/168 2-wire Serial

Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 27-1.

Table 26-2.

Oscillator Tolerance Before and After re-Synchronization Algorithm

(2.7V<V

CC<5.5V, -40°C to +125°C)

Parameter

Clock Tolerance

ΔF/F

Master

FTOL_UNSYNCH

Deviation of slave node clock from the nominal clock rate before

synchronization; relevant for nodes making use of

synchronization and direct SYNCH BREAK detection.

±14.0 %

TOL_SYNCH

Deviation of slave node clock relative to the master node clock

after synchronization; relevant for nodes making use of

synchronization; any slave node must stay within this tolerance

for all fields of a frame which follow the SYNCH FIELD.

Note: For communication between any two nodes their bit rate

must not differ by more than ±2%.

±2.0 %

Table 27-1.

2-wire Serial Bus Requirements

Symbol

Parameter

Condition

Min

Max

Units

VIL

Input Low-voltage

-0.5

0.3 VCC

VIH

Input High-voltage

0.7 V

CC + 0.5

Vhys

(1)

Hysteresis of Schmitt Trigger Inputs

0.05 VCC

(2)

–V

VOL

(1)

Output Low-voltage

3 mA sink current

0.4

(1)

Rise Time for both SDA and SCL

20 + 0.1C

(3)(2)

300

tof

(1)

Output Fall Time from VIHmin to VILmax

10 pF < Cb < 400 pF

(3)

20 + 0.1Cb

(3)(2)

250

tSP

(1)

Spikes Suppressed by Input Filter

50(2)

Input Current each I/O Pin

0.1V

CC < Vi < 0.9VCC

-10

µA

(1)

Capacitance for each I/O Pin

–

fSCL

SCL Clock Frequency

fCK

(4) > max(16f

SCL, 250kHz)

(5)

400

kHz

Value of Pull-up resistor

SCL ≤100 kHz

SCL > 100 kHz

HD;STA

Hold Time (repeated) START Condition

SCL ≤100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

tLOW

Low Period of the SCL Clock

SCL ≤100 kHz

(6)

4.7

–

µs

SCL > 100 kHz

(7)

1.3

–

µs

VCC 0,4V

–

3mA

----------------------------

1000ns

-------------------

VCC 0,4V

–

3mA

----------------------------

300ns

----------------

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