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ATmega88 Datasheet(PDF) 305 Page - ATMEL Corporation |
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ATmega88 Datasheet(HTML) 305 Page - ATMEL Corporation |
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305 / 340 page  305 7530H–AVR–02/09 ATmega48/88/168 Automotive 27.1 SPI Timing Characteristics See Figure 27-2 and Figure 27-3 for details. Note: 1. In SPI Programming mode the minimum SCK high/low period is: - 2 t CLCL for fCK < 12 MHz - 3 tCLCL for fCK > 12 MHz Figure 27-2. SPI Interface Timing Requirements (Master Mode) Table 27-2. SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 16-4 ns 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.5 • tsck 7 SCK to out Master 10 8 SCK to out high Master 10 9SS low to out Slave 15 10 SCK period Slave 4 • tck 11 SCK high/low(1) Slave 2 • tck 12 Rise/Fall time Slave 1600 13 Setup Slave 10 14 Hold Slave tck 15 SCK to out Slave 15 16 SCK to SS high Slave 20 17 SS high to tri-state Slave 10 18 SS low to SCK Slave 20 MOSI (Data Output) SCK (CPOL = 1) MISO (Data Input) SCK (CPOL = 0) SS MSB LSB LSB MSB ... ... 61 22 3 45 8 7 |
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