ADP3210 datasheet(16/38 Pages) ONSEMI

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ADP3210

Rev. 0.3 | Page 16 of 38

IR = AR ×IRAMP

0.2V

CLOCK

OSCILLATOR

FLIP-FLOP

IR = AR × IRAMP

0.2V

CLOCK

OSCILLATOR

FLIP-FLOP

VCC

LOAD

SW1

PWM1

VCC

DRVH

DRVL

GATE DRIVER

DRVH

DRVL

GATE DRIVER

SW2

VCC

RAMP

CFB

RFB

VDC

VCS

RCS

CCS

RPH

COMP

FBRTN

CSCOMP

CSSUM

CSREF

LLINE

+–

–

PWM2

IR = AR ×IRAMP

0.2V

CLOCK

OSCILLATOR

FLIP-FLOP

IR = AR × IRAMP

0.2V

CLOCK

OSCILLATOR

FLIP-FLOP

VCC

LOAD

SW1

PWM1

VCC

DRVH

DRVL

GATE DRIVER

DRVH

DRVL

GATE DRIVER

DRVH

DRVL

GATE DRIVER

DRVH

DRVL

GATE DRIVER

SW2

VCC

RAMP

CFB

RFB

VDC

VCS

RCS

CCS

RPH

COMP

FBRTN

CSCOMP

CSSUM

CSREF

LLINE

+–

–

PWM2

Figure 9. Dual-Phase PWM Mode Operation

SWITCH FREQUENCY SETTING

Master Clock Frequency for PWM Mode

The clock frequency of the ADP3210 is set by an external

resistor connected from the RT pin to ground. The frequency

varies with the VID voltage: the lower the VID voltage, the

lower the clock frequency. The variation of clock frequency

with VID voltage makes VCORE ripple remain constant and

improves power conversion efficiency at a lower VID voltage.

Figure 6 shows the relationship between clock frequency and

VID voltage, parameterized by RT resistance.

To determine the switching frequency per phase, the clock is

divided by the number of phases in use. If PWM3 is pulled up

to VCC, then the master clock is divided by 2 for the frequency

of the remaining phases. If PWM2 and PWM3 are pulled up to

VCC, then the switching frequency of a Phase 1 equals the

master clock frequency. If all phases are in use, divide by 3.

Switching Frequency for RPM Mode–Phase 1

When ADP3210 operates in single-phase RPM mode, its

switching frequency is not controlled by the master clock, but

by the ripple voltage on the COMP pin. The PWM1 pin is set

high each time the COMP pin voltage rises to a voltage limit

determined by the VID voltage and the external resistance

connected from Pin RPM to ground. Whenever PWM1 pin is

high, an internal ramp signal rises at a slew rate programmed by

the current flowing into the RAMP pin. Once this internal

ramp signal hits the COMP pin voltage, the PWM1 pin is reset

to low.

In continuous current mode, the switching frequency of RPM

operation is maintained almost constantly. While in

discontinuous current mode, the switching frequency reduces

with the load current.

OUTPUT VOLTAGE DIFFERENTIAL SENSING

The ADP3210 combines differential sensing with a high accuracy,

VID DAC, precision REF output and a low offset error amplifier to

meet the rigorous accuracy requirement of the Intel IMVP-6.5

specification. In steady-state, the VID DAC and error amplifier

meet the worst-case error specification of ±10 mV over the full

operating output voltage and temperature range.

The CPU core output voltage is sensed between the FB and

FBRTN pins. Connect FB through a resistor to the positive

regulation point, usually the VCC remote sense pin of the

microprocessor. Connect FBRTN directly to the negative

remote sense point, the VSS sense point of the CPU. The

internal VID DAC and precision voltage reference are

ADP3210 Datasheet(PDF) 16 Page - ON Semiconductor

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