LPC2103 datasheet(20/37 Pages) NXP

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LPC2101_02_03_4

Product data sheet

Rev. 04 — 2 June 2009

20 of 37

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.

Peripheral functions continue operation during Idle mode and may generate interrupts to

cause the processor to resume execution. Idle mode eliminates power used by the

processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Power-down mode and the logic levels of chip output pins remain

static. The Power-down mode can be terminated and normal operation resumed by either

a reset or certain speciﬁc interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Power-down mode reduces chip power

consumption to nearly zero.

Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip

RTC will enable the microcontroller to have the RTC active during Power-down mode.

Power-down current is increased with RTC active. However, it is signiﬁcantly lower than in

Idle mode.

In Deep-power down mode all power is removed from the internal chip logic except for the

RTC module, the I/O ports, the SRAM, and the 32 kHz external oscillator. For additional

power savings, SRAM and the 32 kHz oscillator can be powered down individually. The

Deep power-down mode produces the lowest possible power consumption without

actually removing power from the entire chip. In Deep power-down mode, the contents of

registers and memory are not preserved except for SRAM, if selected, and three general

purpose registers. Therefore, to resume operations, a full chip reset process is required.

A power selector module switches the RTC power supply from VBAT to VDD(1V8) whenever

the core voltage is present on pin VDD(1V8) to conserve battery power.

A power control for peripherals feature allows individual peripherals to be turned off if they

are not needed in the application, resulting in additional power savings during Active and

Idle mode.

6.17.8 APB

The APB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The APB divider serves two purposes. The ﬁrst

is to provide peripherals with the desired PCLK via APB so that they can operate at the

speed chosen for the ARM processor. In order to achieve this, the APB may be slowed

down to 1

⁄

2 to

⁄

4 of the processor clock rate. Because the APB must work properly at

power-up (and its timing cannot be altered if it does not work since the APB divider control

registers reside on the APB), the default condition at reset is for the APB to run at 1

⁄

4 of the

processor clock rate. The second purpose of the APB divider is to allow power savings

when an application does not require any peripherals to run at the full processor rate.

Because the APB divider is connected to the PLL output, the PLL remains active (if it was

running) during Idle mode.

6.18 Emulation and debugging

The LPC2101/02/03 support emulation and debugging via a JTAG serial port.

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