PCA9501 datasheet(17/28 Pages) NXP

17 / 28 page

PCA9501_4

Product data sheet

Rev. 04 — 10 February 2009

17 of 28

NXP Semiconductors

PCA9501

8-bit I2C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM

12. Dynamic characteristics

[1]

All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input

voltage swing of VSS to VDD.

[2]

tpu(R) and tpu(W) are the delays required from the time VDD is stable until the speciﬁed operation can be initiated. These parameters are

guaranteed by design.

[3]

Tcy(W) is the maximum time that the device requires to perform the internal write operation.

Table 6.

Dynamic characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I2C-bus timing[1] (see Figure 24)

fSCL

SCL clock frequency

400

kHz

tSP

pulse width of spikes that must be

suppressed by the input ﬁlter

tBUF

bus free time between a STOP and START

condition

1.3

µs

tSU;STA

set-up time for a repeated START condition

0.6

µs

tHD;STA

hold time (repeated) START condition

0.6

µs

rise time of both SDA and SCL signals

0.3

µs

fall time of both SDA and SCL signals

0.3

µs

tSU;DAT

data set-up time

250

tHD;DAT

data hold time

tVD;DAT

data valid time

SCL LOW to

data output

1.0

µs

tSU;STO

set-up time for STOP condition

0.6

µs

Port timing

tv(Q)

data output valid time

CL ≤ 100 pF

µs

tsu(D)

data input set-up time

CL ≤ 100 pF

µs

th(D)

data input hold time

CL ≤ 100 pF

µs

Interrupt timing

tv(INT)

valid time on pin INT

CL ≤ 100 pF

µs

trst(INT)

reset time on pin INT

CL ≤ 100 pF

µs

Power-up timing

tpu(R)

read power-up time

[2] --1

tpu(W)

write power-up time

[2] --5

Write cycle limits (see Figure 25)

Tcy(W)

write cycle time

[3] -

Table 7.

Non-volatile storage speciﬁcations

Parameter

Speciﬁcation

memory cell data retention

10 years minimum

number of memory cell write cycles

100,000 cycles minimum

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