| Electronic Components Datasheet Search |
|
PCA9501 Datasheet(PDF) 7 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
PCA9501 Datasheet(HTML) 7 Page - NXP Semiconductors |
|
7 / 28 page ![]() PCA9501_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 10 February 2009 7 of 28 NXP Semiconductors PCA9501 8-bit I2C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM 7.3.1 Quasi-bidirectional I/Os A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. See Figure 9. 7.3.2 Interrupt The PCA9501 provides an open-drain output (INT) which can be fed to a corresponding input of the microcontroller. This gives these chips a type of master function which can initiate an action elsewhere in the system. See Figure 10. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tv(INT) the signal INT is valid. See Figure 11. Resetting and reactivating the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from or written to the port which has generated the interrupt. Resetting occurs as follows: • In the Read mode at the acknowledge bit after the rising edge of the SCL signal • In the Write mode at the acknowledge bit after the HIGH-to-LOW transition of the SCL signal • Returning of the port data to its original setting • Interrupts which occur during the acknowledge clock pulse may be lost (or very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting will be detected and, after the next rising clock edge, will be transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit. Fig 9. Transient pull-up current (IOHt) while IO3 changes from LOW to HIGH and back to LOW 0 A S slave address (I/O expander) START condition R/W acknowledge from slave 002aad292 1 data to port A acknowledge from slave 12345678 SCL 9 SDA 0 A IO3 output voltage IO3 pull-up output current acknowledge from slave data to port A5 A4 A3 A2 A1 A0 0 IO3 P STOP condition IO3 IOHt IOH |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |