PCA9501_4

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 04 — 10 February 2009

9 of 28

NXP Semiconductors

PCA9501

7.4.1.2

Page write

A page write is initiated in the same way as the byte write, if after sending the first word of

data the STOP condition is not received, the PCA9501 considers subsequent words as

data. After each data word the PCA9501 responds with an acknowledge and the four least

significant bits of the memory address field are incremented. Should the master not send

a STOP condition after 16 data words, the address counter will return to its initial value

and overwrite the data previously written. After the receipt of the STOP condition the

inputs will behave as with the byte write during the internal write cycle.

7.4.2 Read operations

PCA9501 read operations are initiated in an identical manner to write operations with the

exception that the memory slave address R/W bit is set to ‘1’. There are three types of

read operations: current address read, random read and sequential read.

7.4.2.1

Current address read

The PCA9501 contains an internal address counter that increments after each read or

write access and as a result, if the last word accessed was at address ‘n’ then the address

counter contains the address ‘n + 1’.

When the PCA9501 receives its memory slave address with the R/W bit set to one it

issues an acknowledge and uses the next eight clocks to transmit the data contained at

the address stored in the address counter. The master ceases the transmission by issuing

the STOP condition after the eighth bit. There is no ninth clock cycle for the acknowledge.

Fig 12. Byte write

0

A

S

slave address (memory)

START condition

R/W

acknowledge

from slave

002aad296

word address

SDA

A5 A4 A3 A2 A1 A0

1

P

STOP condition.

Write to the memory

is performed.

A

acknowledge

from slave

data

A

acknowledge

from slave

Fig 13. Page write

0

A

S

slave address (memory)

START condition

R/W

acknowledge

from slave

002aad297

word address

SDA

A5 A4 A3 A2 A1 A0

1

P

STOP condition.

Write to the memory is performed.

A

acknowledge

from slave

data to memory

A

acknowledge

from slave

DATA n

data to memory

A

acknowledge

from slave

DATA n + 3