PCA9501 datasheet(5/28 Pages) NXP

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PCA9501_4

Product data sheet

Rev. 04 — 10 February 2009

5 of 28

NXP Semiconductors

PCA9501

8-bit I2C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM

Functional description

Refer also to Figure 1 “Block diagram of PCA9501”.

7.1 Device addressing

Following a START condition, the bus master must output the address of the slave it is

accessing. The address of the PCA9501 is shown in Figure 6. Internal pull-up resistors

are incorporated on the hardware-selectable address pins.

The last bit of the address byte deﬁnes the operation to be performed. When set to logic 1

a read is selected, while a logic 0 selects a write operation.

Remark: Reserved I2C-bus addresses must be used with caution since they can interfere

with:

• Reserved for future use I2C-bus addresses (0000 011, 1111 1xx)

• Slave devices that use the 10-bit addressing scheme (1111 0xx)

• Slave devices that are designed to respond to the General Call address (0000 000)

• Hs-mode master code (0000 1xx)

Fig 5.

Simpliﬁed schematic diagram of each I/O

002aac001

write pulse

read pulse

power-on reset

data from shift register

100

µA

VDD

IO0 to IO7

VSS

data to shift register

to interrupt logic

a. I/O expander

b. Memory

Fig 6.

PCA9501 slave addresses

002aac002

A0 R/W

fixed

slave address

hardware programmable

002aac003

A0 R/W

fixed

slave address

hardware programmable

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