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LTM4611 Datasheet(PDF) 23 Page - Linear Technology

Part # LTM4611
Description  Ultralow VIN, 15A DC/DC 關Module Regulator
PDF  28 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTM4611 Datasheet(HTML) 23 Page - Linear Technology

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LTM4611

4611f
Safety Considerations
The LTM4611 modules do not provide galvanic isolation
from VIN to VOUT. There is no internal fuse. If required,
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure. The device does support overvoltage
protection and overcurrent protection.
Layout Checklist/Example
The high integration of LTM4611 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout consid-
erations are still necessary.
• Use large PCB copper areas for high current paths,
including VIN, GND and VOUT. It helps to minimize the
PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capaci-
tors next to the VIN, GND and VOUT pins to minimize
high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put vias directly on the pad, unless they are
capped or plated over.
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to GND underneath the unit.
• For parallel modules, tie the respective COMP, VFB,
VOUT_LCL, TRACK/SS and RUN pins together. Use an
internal layer to closely connect these pins together.
Figure 17 gives a good example of the recommended
layout. Figures 18 and 19 show schematics of the
LTM4611 devices operating in parallel.
• To facilitate stuffing verification, test and debug activi-
ties, consider routing control signals of the LTM4611
with short traces to localized test points, test pads or
test vias–as PCB layout space permits. Both in-house
and contract manufacturers enjoy gaining electrical
access to all non low impedance (>10Ω) pins of an
IC or µModule device to improve in-circuit test (ICT)
coverage.
Figure 17. Recommended PCB Layouts
GND
VIN
4611 F17
CONTROL
SIGNAL
GROUND
VOUT
VOUT
COUT
COUT
CIN
CIN
applicaTions inForMaTion



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