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GP [ ]asinput

n m

GP [ ]asoutput

n m

GP [ ]asinput

n m

AM1705

SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010

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Table 6-9. GPIO Registers (continued)

BYTE ADDRESS

ACRONYM

0x01E2 60A8

CLR_FAL_TRIG67

GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register

0x01E2 60AC

INTSTAT67

GPIO Banks 6 and 7 Interrupt Status Register

6.9.2

GPIO Peripheral Input/Output Electrical Data/Timing

Table 6-10. Timing Requirements for GPIO Inputs(1) (see Figure 6-10)

No.

PARAMETER

MIN

MAX

UNIT

tw(GPIH)

Pulse duration, GPn[m] as input high

2C(1) (2)

tw(GPIL)

Pulse duration, GPn[m] as input low

2C(1) (2)

(1)

The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the device

recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow the device

enough time to access the GPIO register through the internal bus.

(2)

C=SYSCLK4 period in ns.

Table 6-11. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs

(see Figure 6-10)

No.

PARAMETER

MIN

MAX

UNIT

tw(GPOH)

Pulse duration, GPn[m] as output high

2C(1) (2)

tw(GPOL)

Pulse duration, GPn[m] as output low

2C(1) (2)

(1)

This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the

GPIO is dependent upon internal bus activity.

(2)

C=SYSCLK4 period in ns.

Figure 6-10. GPIO Port Timing

6.9.3

GPIO Peripheral External Interrupts Electrical Data/Timing

Table 6-12. Timing Requirements for External Interrupts(1) (see Figure 6-11)

No.

PARAMETER

MIN

MAX

UNIT

tw(ILOW)

Width of the external interrupt pulse low

2C(1) (2)

tw(IHIGH)

Width of the external interrupt pulse high

2C (1) (2)

(1)

The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have device recognize the

GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow the device enough time to

access the GPIO register through the internal bus.

(2)

C=SYSCLK4 period in ns.

Figure 6-11. GPIO External Interrupt Timing

Peripheral Information and Electrical Specifications

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