AM1705 datasheet(97/156 Pages) TI

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AM1705

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SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010

Table 6-50. General Timing Requirements for SPI0 Slave Modes(1)

No.

PARAMETER

MIN

MAX

UNIT

greater of 2P or

tc(SPC)S

Cycle Time, SPI0_CLK, All Slave Modes

256P

20 ns

tw(SPCH)S

Pulse Width High, SPI0_CLK, All Slave Modes

tw(SPCL)S

Pulse Width Low, SPI0_CLK, All Slave Modes

Polarity = 0, Phase = 0,

to SPI0_CLK rising

Polarity = 0, Phase = 1,

Setup time, transmit data written to SPI

to SPI0_CLK rising

tsu(SOMI_SPC)S

before initial clock edge from master.(2)

Polarity = 1, Phase = 0,

(3)

to SPI0_CLK falling

Polarity = 1, Phase = 1,

to SPI0_CLK falling

Polarity = 0, Phase = 0,

18.5

from SPI0_CLK rising

Polarity = 0, Phase = 1,

18.5

Delay, subsequent bits valid on

from SPI0_CLK falling

td(SPC_SOMI)S

SPI0_SOMI after transmit edge of

Polarity = 1, Phase = 0,

SPI0_CLK

18.5

from SPI0_CLK falling

Polarity = 1, Phase = 1,

18.5

from SPI0_CLK rising

Polarity = 0, Phase = 0,

0.5tc(SPC)S -3

from SPI0_CLK falling

Polarity = 0, Phase = 1,

0.5tc(SPC)S -3

from SPI0_CLK rising

Output hold time, SPI0_SOMI valid afte

toh(SPC_SOMI)S

receive edge of SPI0_CLK

Polarity = 1, Phase = 0,

0.5tc(SPC)S -3

from SPI0_CLK rising

Polarity = 1, Phase = 1,

0.5tc(SPC)S -3

from SPI0_CLK falling

Polarity = 0, Phase = 0,

to SPI0_CLK falling

Polarity = 0, Phase = 1,

to SPI0_CLK rising

Input Setup Time, SPI0_SIMO valid

tsu(SIMO_SPC)S

before receive edge of SPI0_CLK

Polarity = 1, Phase = 0,

to SPI0_CLK rising

Polarity = 1, Phase = 1,

to SPI0_CLK falling

Polarity = 0, Phase = 0,

from SPI0_CLK falling

Polarity = 0, Phase = 1,

from SPI0_CLK rising

Input Hold Time, SPI0_SIMO valid after

tih(SPC_SIMO)S

receive edge of SPI0_CLK

Polarity = 1, Phase = 0,

from SPI0_CLK rising

Polarity = 1, Phase = 1,

from SPI0_CLK falling

(1)

P = SYSCLK2 period

(2)

First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on

SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.

(3)

Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus

cycles must be accounted for to allow data to be written to the SPI module by the CPU.

Peripheral Information and Electrical Specifications

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