AM1705 datasheet(95/156 Pages) TI

95 / 156 page

AM1705

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SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010

6.18.1 SPI Peripheral Registers Description(s)

Table 6-48 is a list of the SPI registers.

Table 6-48. SPIx Configuration Registers

SPI0

SPI1

ACRONYM

BYTE ADDRESS

0x01C4 1000

0x01E1 2000

SPIGCR0

Global Control Register 0

0x01C4 1004

0x01E1 2004

SPIGCR1

Global Control Register 1

0x01C4 1008

0x01E1 2008

SPIINT0

Interrupt Register

0x01C4 100C

0x01E1 200C

SPILVL

Interrupt Level Register

0x01C4 1010

0x01E1 2010

SPIFLG

Flag Register

0x01C4 1014

0x01E1 2014

SPIPC0

Pin Control Register 0 (Pin Function)

0x01C4 1018

0x01E1 2018

SPIPC1

Pin Control Register 1 (Pin Direction)

0x01C4 101C

0x01E1 201C

SPIPC2

Pin Control Register 2 (Pin Data In)

0x01C4 1020

0x01E1 2020

SPIPC3

Pin Control Register 3 (Pin Data Out)

0x01C4 1024

0x01E1 2024

SPIPC4

Pin Control Register 4 (Pin Data Set)

0x01C4 1028

0x01E1 2028

SPIPC5

Pin Control Register 5 (Pin Data Clear)

0x01C4 102C

0x01E1 202C

Reserved

Reserved - Do not write to this register

0x01C4 1030

0x01E1 2030

Reserved

Reserved - Do not write to this register

0x01C4 1034

0x01E1 2034

Reserved

Reserved - Do not write to this register

0x01C4 1038

0x01E1 2038

SPIDAT0

Shift Register 0 (without format select)

0x01C4 103C

0x01E1 203C

SPIDAT1

Shift Register 1 (with format select)

0x01C4 1040

0x01E1 2040

SPIBUF

Buffer Register

0x01C4 1044

0x01E1 2044

SPIEMU

Emulation Register

0x01C4 1048

0x01E1 2048

SPIDELAY

Delay Register

0x01C4 104C

0x01E1 204C

SPIDEF

Default Chip Select Register

0x01C4 1050

0x01E1 2050

SPIFMT0

Format Register 0

0x01C4 1054

0x01E1 2054

SPIFMT1

Format Register 1

0x01C4 1058

0x01E1 2058

SPIFMT2

Format Register 2

0x01C4 105C

0x01E1 205C

SPIFMT3

Format Register 3

0x01C4 1060

0x01E1 2060

Reserved

Reserved - Do not write to this register

0x01C4 1064

0x01E1 2064

INTVEC1

Interrupt Vector for SPI INT1

Peripheral Information and Electrical Specifications

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