AM1705 datasheet(69/156 Pages) TI

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AM1705

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SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010

6.12.2 EMIFB Electrical Data/Timing

Table 6-24. EMIFB SDRAM Interface Timing Requirements

No.

PARAMETER

MIN

MAX

UNIT

tsu(DV-CLKH)

Input setup time, read data valid on EMB_D[31:0] before EMB_CLK rising

0.8

th(CLKH-DIV)

Input hold time, read data valid on EMB_D[31:0] after EMB_CLK rising

1.5

Table 6-25. EMIFB SDRAM Interface Switching Characteristics

No.

PARAMETER

MIN

MAX

UNIT

tc(CLK)

Cycle time, EMIF clock EMB_CLK

7.5

tw(CLK)

Pulse width, EMIF clock EMB_CLK high or low

td(CLKH-CSV)

Delay time, EMB_CLK rising to EMB_CS[0] valid

5.1

toh(CLKH-CSIV)

Output hold time, EMB_CLK rising to EMB_CS[0] invalid

0.9

td(CLKH-DQMV)

Delay time, EMB_CLK rising to EMB_WE_DQM[3:0] valid

5.1

toh(CLKH-DQMIV)

Output hold time, EMB_CLK rising to EMB_WE_DQM[3:0] invalid

0.9

td(CLKH-AV)

Delay time, EMB_CLK rising to EMB_A[12:0] and EMB_BA[1:0] valid

5.1

toh(CLKH-AIV)

Output hold time, EMB_CLK rising to EMB_A[12:0] and EMB_BA[1:0] invalid

0.9

td(CLKH-DV)

Delay time, EMB_CLK rising to EMB_D[31:0] valid

5.1

toh(CLKH-DIV)

Output hold time, EMB_CLK rising to EMB_D[31:0] invalid

0.9

td(CLKH-RASV)

Delay time, EMB_CLK rising to EMB_RAS valid

5.1

toh(CLKH-RASIV)

Output hold time, EMB_CLK rising to EMB_RAS invalid

0.9

td(CLKH-CASV)

Delay time, EMB_CLK rising to EMB_CAS valid

5.1

toh(CLKH-CASIV)

Output hold time, EMB_CLK rising to EMB_CAS invalid

0.9

td(CLKH-WEV)

Delay time, EMB_CLK rising to EMB_WE valid

5.1

toh(CLKH-WEIV)

Output hold time, EMB_CLK rising to EMB_WE invalid

0.9

tdis(CLKH-DHZ)

Delay time, EMB_CLK rising to EMB_D[31:0] 3-stated

5.1

tena(CLKH-DLZ)

Output hold time, EMB_CLK rising to EMB_D[31:0] driving

0.9

Peripheral Information and Electrical Specifications

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