Xin

Xout

Vctr

VCXO

XO

i.e.

XCSEL =10pF

6pF*

20pF

2pF*

*InputCapacitance

C1

C2

20pF

CDCE937

CDCEL937

SLAS564F – AUGUST 2007 – REVISED MARCH 2010

www.ti.com

Table 9. Generic Configuration Register

Offset

(1)

Bit

(2)

Acronym

Default

(3)

Description

7

E_EL

Xb

Device identification (read-only): 1 is CDCE937 (3.3 V), 0 is CDCEL937 (1.8 V)

00h

6:4

RID

Xb

Revision Identification Number (read only)

3:0

VID

1h

Vendor Identification Number (read only)

7

–

0b

Reserved – always write 0

EEPROM Programming Status:

0 – EEPROM programming is completed

6

EEPIP

0b

1 – EEPROM is in programming mode

Permanently Lock EEPROM Data

(5)

0 – EEPROM is not locked

5

EELOCK

0b

1 – EEPROM will be permanently locked

01h

Device Power Down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)

Note: PWDN cannot be set to 1 in the EEPROM.

4

PWDN

0b

0 – device active (PLL1 and all outputs are enabled)

1 – device power down (PLL1 in power down and all outputs in 3-state)

3:2

INCLK

00b

Input clock selection:

00 – Xtal

01 – VCXO

10 – LVCMOS

11 – reserved

1:0

SLAVE_ADR

01b

Programmable Address Bits A0 and A1 of the Slave Receiver Address

7

M1

1b

Clock source selection for output Y1:

0 – input clock

1 – PLL1 clock

Operation mode selection for pin 18/19

(6)

6

SPICON

0b

0 – serial programming interface SDA (pin 19) and SCL (pin 18)

1 – control pins S1 (pin 19) and S2 (pin 18)

02h

5:4

Y1_ST1

11b

Y1-State0/1 Definition

00 – device power down (all PLLs in power down and all outputs in 3-State)

10 – Y1 disabled to low

3:2

Y1_ST0

01b

01 – Y1 disabled to 3-state

11 – Y1 enabled

1:0

Pdiv1 [9:8]

10-Bit Y1-Output-Divider Pdiv1:

0 – divider reset and stand-by

001h

1-to-1023 – divider value

03h

7:0

Pdiv1 [7:0]

7

Y1_7

0b

Y1_ST0/Y1_ST1 State Selection

(7)

6

Y1_6

0b

0 – State0 (predefined by Y1_ST0)

1 – State1 (predefined by Y1_ST1)

5

Y1_5

0b

4

Y1_4

0b

04h

3

Y1_3

0b

2

Y1_2

0b

1

Y1_1

1b

0

Y1_0

0b

Crystal Load Capacitor

00h

→ 0 pF

Selection

(8)

01h

→ 1 pF

02h

→ 2 pF

7:3

XCSEL

0Ah

:

05h

14h-to-1Fh

→ 20 pF

2:0

0b

Reserved – do not write other than 0

7-Bit Byte Count (defines the number of bytes which will be sent from this device at the next Block Read transfer); all bytes have to

7:1

BCOUNT

40h

be read out to correctly finish the read cycle.)

06h

0– no EEPROM write cycle

Initiate EEPROM Write Cycle

(4) (9)

0

EEWRITE

0b

1 – start EEPROM write cycle (internal configuration register is saved to the EEPROM)

(1)

Writing data beyond ‘40h’ may affect device function.

(2)

All data transferred with the MSB first.

(3)

Unless customer-specific setting.

(4)

During EEPROM programming, no data is allowed to be sent to the device via the SDA/SCL bus until the programming sequence is

completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read).

(5)

If this bit is set to high in the EEPROM, the actual data in the EEPROM will be permanently locked. There is no further programming

possible. Data, however can still be written via SDA/SCL bus to the internal register to change device function on the fly. But new data

can no longer be saved to the EEPROM. EELOCK is effective only, if written into the EEPROM!

(6)

Selection of “control pins” is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are

(SDA/SCL), and the two slave receiver address bits are reset to A0=”0” and A1=“0”.

(7)

These are the bits of the Control Terminal Register. The user can predefine up to eight different control settings. These settings then

can be selected by the external control pins, S0, S1, and S2.

(8)

The internal load capacitor (C1, C2) has to be used to achieve the best clock performance. External capacitors should be used only to

application report SCAA085.

(9)

Note: The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The

EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level high does not trigger an EEPROM WRITE cycle. The

EEWRITE bit has to be reset to low after the programming is completed. The programming status can be monitored by reading out

EEPIP. If EELOCK is set to high, no EEPROM programming is possible.

16

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