CDCE937

CDCEL937

SLAS564F – AUGUST 2007 – REVISED MARCH 2010

www.ti.com

REVISION HISTORY

Changes from Original (August 2007) to Revision A

Page

•

Changed from the device status Product preview to Production. ......................................................................................... 1

Changes from Revision A (September 2007) to Revision B

Page

•

Changed Terminal Functions Table - the pin numbers to correpond with pin outs on the package .................................... 2

•

Changed the PACKAGE THERMAL RESISTANCE table .................................................................................................... 4

•

Changed Table 9 RID default From: 0h To: Xb .................................................................................................................. 16

•

Added note to PWDN description, Table 9 ......................................................................................................................... 16

Changes from Revision B (December 2007) to Revision C

Page

•

Changed Table 9 - SLAVE_ADR default value From: 00b To: 01b ................................................................................... 16

Changes from Revision C (January 2009) to Revision D

Page

•

Added Note 3: SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table ................... 3

Changes from Revision D (September 2009) to Revision E

Page

•

Deleted sentence - A different default setting can be programmed on customer request. Contact Texas Instruments

sales or marketing representative for more information. .................................................................................................... 11

Changes from Revision E (October 2009) to Revision F

Page

•

Added PLL settings limits: 16

≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096 foot to PLL1, PLL2, and PLL3 Configure Register

Table ................................................................................................................................................................................... 18

•

Added PLL settings limits: 16

≤q≤63, 0≤p≤7, 0≤r≤511 to PLL Multiplier/Divider Definition Section .................................... 23

24

Submit Documentation Feedback

Copyright © 2007–2010, Texas Instruments Incorporated

Product Folder Link(s): CDCE937 CDCEL937