CDCE937

CDCEL937

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SLAS564F – AUGUST 2007 – REVISED MARCH 2010

Table 11. PLL2 Configuration Register

Acronym

DESCRIPTION

7:5

SSC2_7 [2:0]

000b

20h

4:2

SSC2_6 [2:0]

000b

Down

Center

000 (off)

000 (off)

1:0

SSC2_5 [2:1]

001 – 0.25%

001 ± 0.25%

000b

010 – 0.5%

010 ± 0.5%

7

SSC2_5 [0]

011 – 0.75%

011 ± 0.75%

6:4

SSC2_4 [2:0]

000b

100 – 1.0%

100 ± 1.0%

21h

101 – 1.25%

101 ± 1.25%

3:1

SSC2_3 [2:0]

000b

110 – 1.5%

110 ± 1.5%

0

SSC2_2 [2]

111 – 2.0%

111 ± 2.0%

000b

7:6

SSC2_2 [1:0]

22h

5:3

SSC2_1 [2:0]

000b

2:0

SSC2_0 [2:0]

000b

7

FS2_7

0b

6

FS2_6

0b

5

FS2_5

0b

4

FS2_4

0b

23h

3

FS2_3

0b

2

FS2_2

0b

1

FS2_1

0b

0

FS2_0

0b

PLL2 Multiplexer:

0 – PLL2

7

MUX2

1b

1 – PLL2 Bypass (PLL2 is in power down)

Output Y4 Multiplexer:

0 – Pdiv2

6

M4

1b

1 – Pdiv4

Output Y5 Multiplexer:

00 – Pdiv2-Divider

01 – Pdiv4-Divider

24h

5:4

M5

10b

10 – Pdiv5-Divider

11 – reserved

3:2

Y4Y5_ST1

11b

Y4,

00 – Y4/Y5 disabled to 3-State (PLL2 is in power down)

Y5-State0/1definition:

01 – Y4/Y5 disabled to 3-State

10–Y4/Y5 disabled to low

1:0

Y4Y5_ST0

01b

11 – Y4/Y5 enabled

7

Y4Y5_7

0b

6

Y4Y5_6

0b

0 – state0 (predefined by Y4Y5_ST0)

1 – state1 (predefined by Y4Y5_ST1)

5

Y4Y5_5

0b

4

Y4Y5_4

0b

25h

3

Y4Y5_3

0b

2

Y4Y5_2

0b

1

Y4Y5_1

1b

0

Y4Y5_0

0b

(1)

Writing data beyond 40h may adversely affect device function.

(2)

All data is transferred MSB-first.

(3)

Unless a custom setting is used

(4)

The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external

control pins, S0, S1, and S2.

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