CDCE937 datasheet(22/30 Pages) TI

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CDCE937

CDCEL937

SLAS564F – AUGUST 2007 – REVISED MARCH 2010

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Table 12. PLL3 Configuration Register (continued)

OFFSET(1)

Bit(2)

Acronym

Default(3)

DESCRIPTION

SSC3DC

PLL3 SSC down/center selection:

0 – down

1 – center

36h

6:0

Pdiv6

01h

7-Bit Y6-Output-Divider Pdiv6:

0 – reset and stand-by

1-to-127 – divider value

—

Reserved – do not write others than 0

37h

6:0

Pdiv7

01h

7-Bit Y7-Output-Divider Pdiv7:

0 – reset and stand-by

1-to-127 – divider value

38h

7:0

PLL3_0N [11:4]

PLL3_0(5): 30-Bit Multiplier/Divider value for frequency fVCO3_0

004h

(for more information see paragraph PLL Multiplier/Divider Definition)

7:4

PLL3_0N [3:0]

39h

3:0

PLL3_0R [8:5]

000h

7:3

PLL3_0R[4:0]

3Ah

2:0

PLL3_0Q [5:3]

10h

7:5

PLL3_0Q [2:0]

4:2

PLL3_0P [2:0]

010b

3Bh

fVCO3_0 range selection:

00 – fVCO3_0 < 125 MHz

01 – 125 MHz

≤ fVCO3_0 < 150 MHz

1:0

VCO3_0_RANGE

00b

10 – 150 MHz

≤ fVCO3_0 < 175 MHz

11 – fVCO3_0 ≥ 175 MHz

3Ch

7:0

PLL3_1N [11:4]

PLL3_1(5): 30-Bit Multiplier/Divider value for frequency fVCO3_1

004h

(for more information see paragraph PLL Multiplier/Divider Definition)

7:4

PLL3_1N [3:0]

3Dh

3:0

PLL3_1R [8:5]

000h

7:3

PLL3_1R[4:0]

3Eh

2:0

PLL3_1Q [5:3]

10h

7:5

PLL3_1Q [2:0]

4:2

PLL3_1P [2:0]

010b

3Fh

fVCO3_1 range selection:

00 – fVCO3_1 < 125 MHz

01 – 125 MHz

≤ fVCO3_1 < 150 MHz

1:0

VCO3_1_RANGE

00b

10 – 150 MHz

≤ fVCO3_1 < 175 MHz

11 – fVCO3_1 ≥ 175 MHz

(5)

PLL settings limits: 16

≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096

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