CDCE937

CDCEL937

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SLAS564F – AUGUST 2007 – REVISED MARCH 2010

Table 9. Generic Configuration Register (continued)

Offset

(1)

Bit

(2)

Acronym

Default

(3)

Description

07h-0Fh

—

0h

Unused address range

Table 10. PLL1 Configuration Register

Acronym

DESCRIPTION

7:5

SSC1_7 [2:0]

000b

10h

4:2

SSC1_6 [2:0]

000b

Down

Center

000 (off)

000 (off)

1:0

SSC1_5 [2:1]

001 – 0.25%

001 ± 0.25%

000b

010 – 0.5%

010 ± 0.5%

7

SSC1_5 [0]

011 – 0.75%

011 ± 0.75%

6:4

SSC1_4 [2:0]

000b

100 – 1.0%

100 ± 1.0%

11h

101 – 1.25%

101 ± 1.25%

3:1

SSC1_3 [2:0]

000b

110 – 1.5%

110 ± 1.5%

0

SSC1_2 [2]

111 – 2.0%

111 ± 2.0%

000b

7:6

SSC1_2 [1:0]

12h

5:3

SSC1_1 [2:0]

000b

2:0

SSC1_0 [2:0]

000b

7

FS1_7

0b

6

FS1_6

0b

5

FS1_5

0b

4

FS1_4

0b

13h

3

FS1_3

0b

2

FS1_2

0b

1

FS1_1

0b

0

FS1_0

0b

0 – PLL1

7

MUX1

1b

PLL1 Multiplexer:

1 – PLL1 Bypass (PLL1 is in power down)

0 – Pdiv1

6

M2

1b

Output Y2 Multiplexer:

1 – Pdiv2

00 – Pdiv1-Divider

01 – Pdiv2-Divider

14h

5:4

M3

10b

Output Y3 Multiplexer:

10 – Pdiv3-Divider

11 – reserved

3:2

Y2Y3_ST1

11b

00 – Y2/Y3 disabled to 3-State (PLL1 is in power down)

01 – Y2/Y3 disabled to 3-State

Y2, Y3-State0/1definition:

10–Y2/Y3 disabled to low

1:0

Y2Y3_ST0

01b

11 – Y2/Y3 enabled

7

Y2Y3_7

0b

6

Y2Y3_6

0b

0 – state0 (predefined by Y2Y3_ST0)

1 – state1 (predefined by Y2Y3_ST1)

5

Y2Y3_5

0b

4

Y2Y3_4

0b

15h

3

Y2Y3_3

0b

2

Y2Y3_2

0b

1

Y2Y3_1

1b

0

Y2Y3_0

0b

(1)

Writing data beyond 40h may adversely affect device function.

(2)

All data is transferred MSB-first.

(3)

Unless a custom setting is used

(4)

The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external

control pins, S0, S1, and S2.

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