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TPS23754PWPR Datasheet(PDF) 8 Page - Texas Instruments

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Part # TPS23754PWPR
Description  High Power/High Efficiency PoE Interface and DC/DC Controller
PDF  41 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS23754PWPR Datasheet(HTML) 8 Page - Texas Instruments

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APD1
APD2
ADPTR_ON
APDEN
APDEN
APD1
APD2
ADPTR_OFF
APDEN
APDH
APD2
R
= R
V
V
V
R
+ R
V
=
V
V
R
´
-
´
-
( )
( )
BLNK
BLNK
R
k
= t
ns
W
TPS23754
TPS23754-1
TPS23756
SLVS885D – OCTOBER 2008 – REVISED DECEMBER 2009
www.ti.com
PIN DESCRIPTION
Refer to Figure 1 for component reference designators (RCS for example), and the Electrical Characteristics table
for values denoted by reference (VCSMAX for example). Electrical Characteristic values take precedence over any
numerical values used in the following sections.
APD
APD forces power to come from an external adapter connected from VDD1 to RTN by opening the hotswap
switch, disabling the CLS output (see PPD pin description), and enabling the T2P output. A resistor divider is
recommended on APD when it is connected to an external adapter. The divider provides ESD protection,
leakage discharge for the adapter ORing diode, and input voltage qualification. Voltage qualification assures the
adapter output voltage is high enough that it can support the PD before the PoE current is cut off.
Select the APD divider resistors per Equation 1 where VADPTR-ON is the desired adapter voltage that enables the
APD function as adapter voltage rises.
(1)
Place the APD pull-down resistor adjacent to the APD pin.
APD should be tied to ARTN when not used.
BLNK
Blanking provides an interval between GATE going high and the current-control comparators on CS actively
monitoring the input. This delay allows the normal turn-on current transient (spike) to subside before the
comparators are active, preventing undesired short duty cycles and premature current limiting.
Connect BLNK to ARTN to obtain the internally set blanking period. Connect a resistor from BLNK to ARTN for a
more accurate, programmable blanking period. The relationship between the desired blanking period and the
programming resistor is defined by Equation 2.
(2)
Place the resistor adjacent to the BLNK pin when it is used.
CLS
A resistor from CLS to VSS programs the classification current per the IEEE standard. The PD power ranges and
corresponding resistor values are listed in Table 1. The power assigned should correspond to the maximum
average power drawn by the PD during operation.
High-power PSEs may perform two classification cycles if Class 4 is presented on the first cycle. The TPS23754
presents the same (resistor programmed) class each cycle per the standard.
Table 1. Class Resistor Selection
POWER AT PD
RESISTOR
CLASS
NOTES
MINIMUM
MAXIMUM
(
Ω)
(W)
(W)
0
0.44
12.95
1270
Minimum may be reduced by pulsed loading. Serves as a catch-all default class.
1
0.44
3.84
243
2
3.84
6.49
137
3
6.49
12.95
90.9
4
12.95
25.5
63.4
Not allowed prior to IEEE 802.3at. Use to indicate a Type 2 PD (high power)
device per IEEE 802.3at.
8
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Copyright © 2008–2009, Texas Instruments Incorporated



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