TPS23754PWPR datasheet(3/41 Pages) TI

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TPS23754

TPS23754-1

TPS23756

www.ti.com

SLVS885D – OCTOBER 2008 – REVISED DECEMBER 2009

RECOMMENDED OPERATING CONDITIONS

(1)

Voltage with respect to VSS (unless otherwise noted)

MIN

NOM

MAX

UNIT

Input voltage range ARTN, COM, PPD, RTN, VDD, VDD1

Input voltage range T2P, VC to [ARTN, COM]

Input voltage range APD, CTL, DT to [ARTN, COM]

Input voltage range CS to [ARTN, COM]

Continuous RTN current (TJ ≤ 125°C)

(2)

825

Sourcing current, VB

2.5

VB capacitance

0.08

μF

RBLNK

350

Ω

Synchronization pulse width input (when used)

Operating junction temperature range, TJ

–40

125

°C

(1)

ARTN and COM tied to RTN.

(2)

This is the minimum current-limit value. Viable systems will be designed for maximum currents below this value with reasonable margin.

IEEE 802.3at permits 600mA continuous loading

DISSIPATION RATINGS

ΨJT

θJP

θJA

MAXIMUM POWER RATING

PACKAGE

°C/W(1)

°C/W

°C/W(2)

°C/W(3)

(W)(4)

PWP (TSSOP-20)

0.607

1.4

32.6

73.8

1.2

(1)

Thermal resistance junction to case top for devices mounted per SLMA002. TJ = TTOP + (ΨJT x PJ)

(2)

See TI document SLMA002C (or latest version) for recommended layout. This is a best case, natural convection number.

(3)

JEDEC method with high-k board (2 signal – 2 plane layers) and power pad not soldered (worst case).

(4)

Based on TI recommended layout and 85°C.

ELECTRICAL CHARACTERISTICS

Unless otherwise noted: CS=COM=APD=CTL=RTN=ARTN, GATE and GAT2 float, RFRS=68.1 kΩ, RBLNK=249 kΩ, DT=VB,

PPD=VSS, T2P open, CVB=CVC=0.1 μF, RDEN=24.9 kΩ, RCLS open, 0 V ≤ (VDD, VDD1) ≤ 57 V, 0 V ≤ VC ≤ 18 V, –40°C ≤ TJ ≤

125°C. Typical specifications are at 25°C.

CONTROLLER SECTION ONLY

[VSS = RTN and VDD=VDD1] or [VSS=RTN=VDD], all voltages referred to [ARTN, COM].

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VC rising ‘754

14.3

15.7

VCUV

VC rising ‘756

8.7

9.3

UVLO

Hysteresis ‘754 (1)

6.2

6.5

6.8

VCUVH

Hysteresis ‘756 (1)

3.3

3.5

3.7

Operating current

VC = 12 V, CTL = VB, RDT = 68.1 kΩ

0.7

0.92

1.2

‘756, VDD1 = 10.2 V, VC(0) = 0 V

175

‘756, VDD1 = 35 V, VC(0) = 0 V

Bootstrap startup time,

tST

CVC = 22 μF

‘754, VDD1 = 19.2 V, VC(0) = 0 V

166

‘754, VDD1 = 35 V, VC(0) = 0 V

158

‘754, VDD1 = 19.2 V, VC = 13.9 V

1.7

3.4

5.5

Startup current source - IVC

‘756, VDD1 = 10.2 V, VC = 8.6 V

0.44

1.06

1.80

‘754, ‘756, VDD1 = 48 V, VC = 0 V

2.7

4.8

6.8

Voltage

6.5 V

≤ VC ≤ 18 V, 0 ≤ IVB ≤ 5 mA

4.8

5.10

5.25

(1)

The hysteresis tolerance tracks the rising threshold for a given device.

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