TPS23754PWPR datasheet(27/41 Pages) TI

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ADPTR_ON

PPDEN

PPD1

PPDEN

PPD

PPD2

18 V

1.55 V

= 32.26 k

1.55 V

5 A

3.01 k

ö æ

÷ ç

- m

PPDEN

ADPTR_ON

PPDEN

PPD1

PPD

PPD2

= V

+ R

= 18.07 V

(

)

(

)

PPDEN

PPDH

ADPTR_OFF

PPDEN

PPDH

PPD1

PPD

PPD2

+ R

= 14.54 V

(

)

RPPD

PPD1

PPD2

24 V

1.1

)

= 19.6 mW

+ R

3.01 k

+ 32.4 k

FRS

17250

(k ) =

= 69

(kHz)

250

TPS23754

TPS23754-1

TPS23756

www.ti.com

SLVS885D – OCTOBER 2008 – REVISED DECEMBER 2009

APD Pin Divider Network, RAPD1, RAPD2

The APD pin can be used to disable the TPS23754 internal hotswap MOSFET giving the adapter source priority

over the PoE source. An example calculation is provided, see literature number SLVA306A.

PPD Pin Divider Network, RPPD1, RPPD2

The PPD pin can be used to override the internal hotswap MOSFET UVLO (VUVLO_R and VUVLO_H) when using

low voltage adapters connected between VDD and VSS. The PPD pin has an internal 5 μA pulldown current

source. As an example, consider the choice of RPPD1 and RPPD2, for a 24 V adapter.

1. Select the startup voltage, VADPTR-ON approximately 75% of nominal for a 24 V adapter. Assuming that the

adapter output is 24 V ± 10%, this provides 15% margin below the minimum adapter operating voltage.

2. Choose VADPTR-ON = 24 V × 0.75 = 18 V

3. Choose RPPD2 = 3.01 kΩ

4. Calculate RPPD1

(a)

(b) Choose RPPD1 = 32.4 kΩ

5. Check PPD turn on and PPD turn off voltages

(a)

(b)

6. Check PPD resistor power consumption.

(a)

(b) Power is acceptable, but resistor values could be increased to reduce the power loss.

Setting Frequency (RFRS) and Synchronization

The converter switching frequency is set by connecting RFRS from the FRS pin to ARTN. The frequency may be

set as high as 1 MHz with some loss in programming accuracy as well as converter efficiency. Synchronization

at high duty cycles may become more difficult above 500 kHz due to the internal oscillator delays reducing the

available on-time. As an example:

1. Assume a desired switching frequency (fSW) of 250 kHz.

2. Compute RFRS:

(a)

(b) Select 69.8 k

Ω.

The TPS23754 may be synchronized to an external clock to eliminate beat frequencies from a sampled system,

or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by

applying a short pulse (TSYNC) of magnitude VSYNC to FRS as shown in Figure 30. RFRS should be chosen so that

the maximum free-running frequency is just below the desired synchronization frequency. The synchronization

pulse terminates the potential on-time period, and the off-time period does not begin until the pulse terminates.

The pulse at the FRS pin should reach between 2.5 V and VB, with a minimum width of 22 ns (above 2.5 V) and

rise/fall times less than 10 ns. The FRS node should be protected from noise because it is high-impedance. An

RT on the order of 100 Ω in the isolated example reduces noise sensitivity and jitter.

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TPS23754PWPR Datasheet(PDF) 27 Page - Texas Instruments

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