Preliminary
11-130
RF2968
Rev A13 010912
11
Register 4 - IF Register 2 (Write-Only)
LPO [1:0]:
TDet [1:0]:
Bit Number
Bit Name
Comments
12-15
N/A
Not Assigned
11
ChopENB
Enables circuitry that significantly reduces the levels of RF PLL comparison
frequency spurious responses.
1: Spur cancellation disabled.
0: Normal mode. Spur cancellation enabled.
10
Div2ENB
Enables an additional divide-by-two operation in the reference divider cir-
cuitry to accommodate the use of a 20MHz- 40MHz crystal or clock. This
allows a migration path to higher reference frequencies.
1: Normal mode. 10, 11, 12, 13, or 20MHz reference clock.
0: Expanded mode. Reference clock is double that allowed in normal mode.
8-9
LPO[1:0]
Determines the function of the low power mode clock (output at pin 7) when
the device is in Sleep mode according to the table below. In non-Sleep
modes, the output is disabled.
5-7
Gain[2:0]
Sets the gain of the transmitter path. The gain is normally programmed
immediately after the register write to enter the WAIT DATA SYNC state in
Power Class 1 applications. Gain is adjustable from 0dBto-28dB in 4dB
steps. [All 0’s indicates high gain (0dB attenuation); all 1’s indicates low gain
(28dB attenuation).] Example: Gain[2:0]= [011] indicates 12dB attenuation.
4
ENSlowAGCB
1: Slow AGC disabled.
0: Normal mode. Slow AGC enabled.
3
N/A
Not Assigned
2
TPL_AC
Selects a path in the RX data DC estimation circuit.
1: Selects the DC estimation path that is AC coupled and which is normally
used for the payload part of packet.
0: Selects the fast DC estimation RX data path normally used for the access
code of packet.
0-1
TDet[1:0]
Sets the receiver gain according to the table below.
LPO[1:0]
Output at LPO (Pin 7)
0X
32kHz clock
1 0
3.2kHz clock
1 1
Clock disabled
TDet[1:0]
VGA Gain (dB)
Filter Gain (dB)
Total Gain (dB)
Step Size (dB)
11
-11
1.5
-9.5
10
4.5
1.5
6.0
15.5
01
4.5
17
21.5
15.5
00
20
17
37.0
15.5
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