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Preliminary
11-135
RF2968
Rev A13 010912
11
State Machine
The RF2968 state machine is clocked with a 1MHz signal which is derived from the reference oscillator. (The mark -
space ratio of this 1MHz clock and its precise frequency are not important.) The inputs and outputs for all the states are
summarized in the table below.
Table 1. State Machine Inputs and Outputs
Notes:
a.
When the inputs try to force the controller into an undefined or illegal state, the state machine will remain in its
present state (e.g., if the present state is IDLE and the inputs try to force the device to TX DATA, the chip will stay in
IDLE mode).
b.
PD_TX goes high after a fixed delay following TXEN going high.
c.
1
µs delay from the PD_PA going low to PD_TX going low.
d.
PD_RX goes high after a fixed delay following RXEN going high.
e.
BPKTCTL must be low to distinguish DATA SYNC from ENABLE PA.
f.
If RXEN =1 when entering IDLE from DISABLE PA, then IDLE is held for 1
µs, after which the state transitions to RX
PLL WAIT.
Inputs
Outputs
Previous State
Present Statea
BnPWR BXTLEN BDATA1 BPKTCTL RXEN TXEN PDXTAL CLRB PDTX PDPA PDRX
X
OFF
0
XXX
X
X
0
0
0
0
0
OFF
PWRON WAIT
1
0
1
X
X
X
1
1
0
0
0
PWRON WAIT
HOLD XTL
1
1
1
X
00
1
1
000
HOLD XTL
IDLE
1
1
X
X
0
0
1
1
0
0
0
IDLE
SLEEP
1
0
X
X
0
0
0
1
000
SLEEP
WAIT XTL
1
1
X
X
0
0
1
1
0
0
0
WAIT XTL
IDLE
1
1
X
X
0
0
1
1
000
IDLE
WAIT DATA SYNC
1
1
X
0e
01
1
1
1b
00
WAIT DATA
DATA SYNC
1
1
X
0e
X
1
1
1
100
DATA SYNC
ENABLE PA
1
1
X
1
X
1
1
1
1
1
0
ENABLE PA
TX DATA
1
1
X
1
X
1
1
1
110
TX DATA
DISABLE PA
1
1
X
0
X
1
1
1
0c
00
DISABLE PA
IDLE
1
1
X
X
Xf
0
1
1
000
IDLE
RX PLL WAIT
1
1
X
X
1
0
1
1
0
0
1d
RX PLL WAIT
RX DATA
1
1
X
X
1
0
1
1
0
0
1
RX DATA
IDLE
1
1
X
X
0
X
1
1
000
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