Preliminary Technical Data

AD5757/AD5737

Rev. PrD | Page 17 of 31

DATA REGISTERS

The input register is 24 bits wide. When writing to a data register the following format must be used:

Table 8.

AD5757/AD5737 Writing to a Data Register

D23 D22

D21

D20

D19

D18

D17

D16

D15 to D0

R/W DUT_AD1

DUT_AD0

DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0

Table 9.

AD5757/AD5737 Input Register Decode

Register

Function

R/W

Indicates a read from or a write to the addressed register.

by the system controller.

DUT_AD1

DUT_AD0

Function

0

0

Addresses Part with Pins AD1=0, AD0=0

0

1

Addresses Part with Pins AD1=0, AD0=1

1

0

Addresses Part with Pins AD1=1, AD0=0

1

1

Addresses Part with Pins AD1=1, AD0=1

DREG2, DREG1,

DREG0

Selects whether a data register or a control register is written to. If a control register is selected, a further decode

of CREG bits is required to select the particular control register, as detailed below.

DREG2

DREG1

DREG0

Function

0

0

0

Write to DAC Data Register (Individual Channel Write)

0

1

0

Write to Gain Register

0

1

1

Write to Gain Register (ALL DACS)

1

0

0

Write to Offset Register

1

0

1

Write to Offset Register (ALL DACS)

1

1

0

Write to Clear Code Register

1

1

1

Write to a Control Register

DAC_AD1, DAC_AD0

These bits are used to decode the DAC channel

DAC_AD1

DAC_AD0

DAC Channel/ Register Address

0

0

DAC A

0

1

DAC B

1

0

DAC C

1

1

DAC D

X

X

These are don’t cares if they are not relevant to the operation being performed.

DAC DATA REGISTER

Table 10. Programming the AD5757 DAC Data Registers

When writing to the AD5757 DAC Data Registers D15-D0 are used for DAC DATA bits. See Table x for input register decode.

MSB

LSB

D23 D22

D21

D20

D19

D18

D17

D16

D15 to D0

R/W DUT_AD1

DUT_AD0

DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 DATA

Table 11. Programming the AD5737 DAC Data Registers

When writing to the AD5737 DAC Data Registers D15-D4 are used for DAC DATA bits. See Table x for input register decode.

MSB

LSB

D23 D22

D21

D20

D19

D18

D17

D16

D15 to D4 D3 D2 D1 D0

R/W DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 DATA

X

X

X

X