AD5757/AD5737

Preliminary Technical Data

Rev. PrD | Page 18 of 31

GAIN REGISTER

The Gain Register stores the Gain Code (M) which is used in the DAC transfer function to calculated the overall DAC input code (see

formula below). The Gain Register is addressed by setting DREG bits to ‘0,1,0’. The DAC address bits select which DAC channel the gain

write is addressed to. It is possible to write the same gain code to all 4 DAC channels at the same time by setting the DREG bits to 011.

The AD5757/AD5737 Gain Register is a 16/12 bit register (bits G15.. G0/G3) and allows the user to adjust the gain of each channel in

steps of 1 LSB as shown in the Table below. For the AD5737, the last 4 bits should be set to 1. The Gain Register coding is straight binary.

In theory the gain can be tuned across the full range of the output. In practice, the maximum recommended gain trim is about 50% of

programmed range in order to maintain accuracy.

Table 12. Programming the AD5757 Gain Register

R/W DUT_

AD1

DUT_

AD0

DREG2 DREG1 DREG0 DAC_

AD1

DAC_

AD0

D15-D0

0

DEVICE ADDRESS

010

DAC Channel Address G15 to G0

Table 13. Programming the AD5737 Gain Register

R/W DUT_

AD1

DUT_

AD0

DREG2 DREG1 DREG0 DAC_

AD1

DAC_

AD0

D15-D4

D3 D2 D1 D0

0

DEVICE ADDRESS

010

DAC Channel Address G15 to G4 1

1

1

1

Table 14. AD5757 Gain Register

Gain Adjustment

G15

G14

G13

G12 to G4

G3

G2

G1

G0

+65535 LSBs

1

1

1

1

1

1

1

1

+65534 LSBs

1

1

1

1

1

1

0

0

-

-

-

-

-

-

-

-

1 LSBs

0

0

0

0

0

0

0

1

0 LSBs

0

0

0

0

0

0

0

0

Table 15. AD5737 Gain Register

Gain Adjustment

G15

G14

G13 to G5

G4

G3

G2

G1

G0

+8192 LSBs

1

1

1

1

X

X

X

X

+8191 LSBs

1

1

1

0

X

X

X

X

-

-

-

-

X

X

X

X

1 LSBs

0

0

0

1

X

X

X

X

0 LSBs

0

0

0

0

X

X

X

X

OFFSET REGISTER

The Offset Register is addressed by setting the DREG BITS to DREG2 =1 DREG1=0, DREG0=0. The DAC address bits select with which

DAC channel the offset write is addressed to. It is possible to write the same offset code to all 4 DAC channels at the same time by setting

the DREG bits to 101. The AD5757/AD5737 offset code is 16/12 bit (bits OF15.. OF0/OF3) and allows the user to adjust the offset of

each channel by −32768/8192 LSBs to +32767/8191 LSBs in steps of 1 LSB as shown in the Table below. For the AD5737, the last 4 bits are

ignored and should be set to zero. The Offset Register coding is straight binary. The default code in the Offset Register is 0x8000/0x800.

This will result in zero offset programmed to the output.

Table 16. Programming the AD5757 Offset Register

R/W DUT_

AD1

DUT_

AD0

DREG2

DREG1

DREG0

DAC_

AD1

DAC_

AD0

D15 to D0

0

DEVICE ADDRESS 100

DAC Channel Address OF15 to OF0

Table 17. Programming the AD5737 Offset Register

R/W DUT_

AD1

DUT_

AD0

DREG2

DREG1

DREG0

DAC_

AD1

DAC_

AD0

D15 to D4

D3

D2

D1

D0

0

DEVICE ADDRESS 100

DAC Channel Address OF15 to OF4 0

0

0

0