ADF7242 datasheet(49/108 Pages) AD

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ADF7242

Rev. 0 | Page 49 of 108

RECEIVER CALIBRATION

The receive path is calibrated each time an RC_RX command is

issued. Figure 84 outlines the synthesizer and receive path

calibration sequence and timing for the IEEE 802.15.4-2006

mode of operation. The calibration step VCO_cal is omitted by

setting Register vco_cal_cfg, Field skip_vco_cal = 15 (0x36F[3:0]),

which is an option if the value of ch_freq[23:0] remains

unchanged during transitions between the PHY_RDY, RX, and

TX states. The synthesizer settling phase is always required

because the PLL bandwidth is optimized differently for RX and

TX operation. The static offset correction phase (OCL_stat) and

dynamic offset correction phase (OCL_dyn) are also mandatory.

0 TO 20

+ 5 + (0 to 20) + n

FRAME

PAYLOAD

ADDRESS

INFORMA-

TION

FRAME

PAYLOAD

ADDRESS

INFORMA-

TION

Figure 83. IEEE 802.15.4-2006 Packet Fields Stored by the Packet Manager in RX_BUFFER

rx_mac_delay

mac_delay_ext

INIT

SYNTH

SETTLING

OCL

DYNAMIC

OCL

STATIC

VCO_cal

18µs

52µs

53µs

10µs

55µs

188µs

192µs

0µs TO 1020µs

SKIPPED IF

FIELD skip_vco_cal = 15

Figure 84. RX Path Calibration, IEEE 802.15.4-2006 Mode

ADF7242 Datasheet(PDF) 49 Page - Analog Devices

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