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ADF7242 Datasheet(PDF) 23 Page - Analog Devices |
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ADF7242 Datasheet(HTML) 23 Page - Analog Devices |
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23 / 108 page  ADF7242 Rev. 0 | Page 23 of 108 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 24 CS 23 MOSI 22 SCLK 21 MISO 20 IRQ1_GP4 19 TRCLK_CKO_GP3 18 IRQ2_TRFS_GP2 NOTES 1. THE EXPOSED PADDLE MUST BE CONNECTED TO GROUND. 17 DT_GP1 1 2 3 4 5 6 7 8 CREGRF1 RBIAS CREGRF2 RFIO1P RFIO1N RFIO2P RFIO2N CREGRF3 ADF7242 TOP VIEW (Not to Scale) Figure 14. Pin Configuration Table 20. Pin Function Descriptions Pin No. Mnemonic Description 1 CREGRF1 Regulated Supply Terminal for RF Section. Connect a 220 nF decoupling capacitor from this pin to GND. 2 RBIAS Bias Resistor 27 kΩ to Ground. 3 CREGRF2 Regulated Supply for RF Section. Connect a 100 pF decoupling capacitor to ground. 4 RFIO1P Differential RF Input Port 1 (Positive Terminal). A 10 nF coupling capacitor is required. 5 RFIO1N Differential RF Input Port 1 (Negative Terminal). A 10 nF coupling capacitor is required. 6 RFIO2P Differential RF Input/Output Port 2 (Positive Terminal). A 10 nF coupling capacitor required. 7 RFIO2N Differential RF Input/Output Port 2 (Negative Terminal). A 10 nF coupling capacitor required. 8 CREGRF3 Regulated Supply for RF Section. Connect a 100 pF decoupling capacitor from this pin to GND. 9 CREGVCO Regulated Supply for VCO Section. Connect a 220 nF decoupling capacitor from this pin to GND. 10 VCOGUARD Guard Trench for VCO Section. Connect to Pin 9 (CREGVCO). 11 CREGSYNTH Regulated Supply for PLL Section. Connect a 220 nF decoupling capacitor from this pin to GND. 12 XOSC26P Terminal 1 of External Crystal and Loading Capacitor. This pin is no connect (NC) when an external oscillator is used. 13 XOSC26N Terminal 2 of External Crystal and Loading Capacitor. Input for external oscillator. 14 DGUARD Guard Trench for Digital Section. Connect to Pin 15 (CREGDIG2). 15 CREGDIG2 Regulated Supply for Digital Section. Connect a 220 nF decoupling capacitor to ground. 16 DR_GP0 SPORT Receive Data Output/General-Purpose IO Port. 17 DT_GP1 SPORT Transmit Data Input/General-Purpose IO Port. 18 IRQ2_TRFS_GP2 Interrupt Request Output 2/Symbol Clock IEEE 802.15.4-2006 Mode/General-Purpose IO Port. 19 TRCLK_CKO_GP3 SPORT Clock Output/General-Purpose IO Port. 20 IRQ1_GP4 Interrupt Request Output1/General-Purpose IO Port. 21 MISO SPI Interface Serial Data Output. 22 SCLK SPI Interface Data Clock Input. 23 MOSI SPI Interface Serial Data Input. 24 CS SPI Interface Chip Select Input (and Wake-Up Signal). 25 TXEN_GP5 External PA Enable Signal/General-Purpose IO Port. 26 RXEN_GP6 External LNA Enable Signal/General-Purpose IO Port. 27 CREGDIG1 Regulated Supply for Digital Section. Connect a 1 nF decoupling capacitor from this pin to ground. 28 XOSC32KP_GP7_ATB1 Terminal 1 of 32 kHz Crystal Oscillator/General-Purpose IO Port/Analog Test Bus 1. |
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