ADF7242 datasheet(71/108 Pages) AD

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ADF7242

Rev. 0 | Page 71 of 108

WUC Configuration and Operation

The wake-up timer can be configured as follows:

•

The clock signal for the timer is taken from the external

32.768 kHz crystal or the internal RC oscillator. This is

selectable via Register tmr_cfg1, Bit sleep_config

(0x317[6:3]).

•

A 3-bit prescaler, which is programmable via Register

tmr_cfg0, Bit timer_prescal (0x316[2:0]) determines the

tick period.

This is followed by a preloadable 16-bit down counter. After the

clock is selected, the reload value for the down counter

(tmr_rld0 and tmr_rld1) and the prescaler values (Register

tmr_cfg0, Bit timer_prescal) can be programmed. When the

clock has been enabled, the counter starts to count down at the

tick rate starting from the reload value. If wake-up interrupts

are enabled, the timer unit generates an interrupt when the

timer value reaches 0x0000. When armed, the wake-up

interrupt triggers a wake-up from sleep.

The reliable generation of wake-up interrupts requires the

WUC timeout flag to be reset immediately after the reload value

has been programmed. To do this, first write 1and then write 0

to Register tmr_ctrl, Field wake_timer_flag_reset. To enable

automatic wake-up from the sleep state, arm the timer unit for

wake-up operation by writing 1 to Register tmr_cfg1, Field

wake_on_timeout. After writing this sequence to the ADF7242,

a sleep command can be issued.

Calibrating the RC oscillator

The RC oscillator is not automatically calibrated. If it is desired

to use the RC oscillator as the clock source for the WUC, the

host MCU should initiate a calibration. This can be performed

at any time in advance of entering the sleep state. To perform a

calibration, the host MCU should

•

Set Register tmr_ctrl, Field wuc_rc_osc_cal = 0

•

Set Register tmr_ctrl, Field wuc_rc_osc_cal = 1

The calibration time is typically 1 ms. When the calibration is

complete Register wuc_32khzosc_status, Field rc_osc_cal_ready

is high. Following calibration, the host MCU can transition to

the SLEEP_BBRAM_RCO sleep state, by following the full

procedure given in the WUC Configuration and Operation

section.

TRANSMIT TEST MODES

The ADF7242 has various transmit test modes that can be used

in IEEE 802.15.4-2006 and GFSK/FSK SPORT modes. These

test modes can be enabled by writing to Register tx_fsk_test

(Location 0x3F0), as described in Table 44. A continuous packet

transmission mode is also available in IEEE 802.15.4-2006 and

GFSK/FSK packet modes. This mode can be enabled using the

following procedure:

An IEEE 80.215.4-2006 or a GFSK/FSK packet with

random payload should be written to TX_BUFFER as

described in the Transmitter section. It is recommended to

use a packet with the maximum length of 127 bytes.

Set Register buffercfg, Field trx_mac_delay = 1.

Set Register buffercfg, Field tx_buffer_mode = 3.

Set Register pkt_cfg, Field skip_synth_settle = 1.

Issue Command RC_TX. The transmitter continuously

transmits the packet stored in TX_BUFFER.

If Command RC_PHY_RDY is issued at any point after

this step, all the preceding configuration registers must be

rewritten to the device before reissuing Command RC_TX.

Note that the transmitter momentarily transmits an RF carrier

between packets due to a finite delay from when the packet

handler finishes transmitting a packet in TX_BUFFER and

going back to transmit the start of TX_BUFFER again.

Table 44. 0x3F0: tx_fsk_test

Bit

Name

R/W

Reset Value

Description

[7:4]

Reserved

R/W

Reserved, set to default.

zero_only

R/W

Transmit 0 only (fCH − fDEV) in GFSK/FSK sport mode.

one_only

R/W

Transmit 1 only (fCH + fDEV) in GFSK/FSK sport mode.

carrier_only

R/W

Transmits unmodulated tone at the programmed frequency fCH.

Reserved

R/W

Reserved, set to default.

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